Reducing the specific on-resistance (R_on,sp) of power MOSFET is critical to lowering the energy consumption of the system^[1−4]. SJ-MOS is now widely used in the high voltage field for breaking the silicon limit and offering a significantly improved trade-off between the specific on-resistance (R_on,sp) and breakdown voltage (BV) compared to the traditional power MOSFET^[5−8]. In the SJ-MOS, alternately arranged P/N pillars replace the N-type drift region of conventional power MOSFETs, and these P/N pillars become fully depleted under ideal charge-balanced conditions. As a result, a higher BV can be achieved, as the drift region exhibits a better voltage-blocking capacity comparable to that of an intrinsic layer. However, performances of SJ-MOS including BV are highly dependent on the charge balance condition between P/N pillars. Unfortunately, deviations causing charge imbalance between P/N pillars are inevitable in the actual manufacturing process^[9−14]. Until now, many studies have been carried out to analyze the influence of charge matching state of P/N pillars on BV of SJ-MOS. It is proved that the SJ-MOS with pillars of higher doping concentration is more severely affected by charge imbalance. Therefore, with the continuous development of SJ-MOS technology, the narrowed process window becomes a more prominent concern as the doping concentration increases.

However, there are few studies on the improvement methods of the process tolerance of SJ-MOS. In this article, a vertical variable doping SJ-MOS (VVD-SJ) with wider fabrication process window compared to the uniformly doping SJ-MOS (UD-SJ) is proposed. In addition to the simulation and theoretical analysis of the process window of static characteristics as well as avalanche tolerance, the experimental results and comparisons between UD-SJ and VVD-SJ will be also carried out.

The half-cell structure and parameter definitions of the proposed VVD-SJ used for Sentaurus simulation are shown in Fig. 1(a). A process simulation approach is used to ensure a better correspondence with the actual device. As shown in Fig. 1(b), the VVD-SJ structure is fabricated by 7 times epitaxy and 6 times ion implantation, creating a fluctuant profile in the P-pillar. The process is fully compatible with the conventional UD-SJ. To facilitate analysis, the same implantation dose is used for every two times of p-type ion implantations, and the impurity concentration in the N-pillar area is also adjusted by ion implantation. Therefore, P and N pillars can be divided into three regions: T, M, and B. a and b represent the rates of variation in the total impurity concentrations of the P-pillars (Q_P) and N-pillars (Q_N) in regions T and B, respectively, relative to those in the region M. The UD-SJ can be obtained when a = b = 0. K_CIB = Q_P/Q_N is defined to characterize the degree of charge imbalance. When K_CIB = 1, which means, Q_P = Q_N, the P pillars and N pillars are in the charge balanced condition. UD-SJ and VVD-SJ are set to the same pillar pitch (w = 6 μm for half-cell) and pillar length (l = 39 μm).

As shown in Fig. 2, under the condition of charge imbalance, BV drops dramatically both for UD-SJ and VVD-SJ. Here, the process window of BV (W_BV) is defined as the range of K_CIB when BV decreases by 10% from its peak (BV_max). The larger the W_BV, the greater the process tolerance of the device. For UD-SJ, its BV_max and W_BV are 701.27 V and [0.81, 1.17], respectively. It can be seen that when a > 0 or b < 0, VVD-SJ has a lower BV_max but a larger W_BV than UD-SJ. When a > 0, the extension of W_BV is on the side of K_CIB > 1. When b < 0, the extension of W_BV is on the side of K_CIB < 1. The larger the absolute values of a and b, the smaller the BV_max, but the larger the W_BV. In contrast, when a < 0 or b > 0, both BV_max and W_BV of VVD-SJ become smaller than those of UD-SJ. The larger the absolute values of a and b, the smaller the BV_max and W_BV. Obviously, the maximum W_BV can be obtained by taking a > 0 and b < 0. For example, when a = 0.2 and b = −0.2, W_BV of the VVD-SJ expands to [0.72, 1.24] at the expense of BV_max dropping to 662.15 V. Compared to UD-SJ, W_BV expands by 44.44% while BV_max only drops by 5.58%.

Since BV is directly related to the electrical field (E-field) distribution in the drift region, the correlation between E-field and charge imbalance is investigated to analyze how doping distribution affects W_BV. In Fig. 3, points A, B, and O correspond to the points A, B, and O in Fig. 1, respectively, representing the peak electric field positions in regions T, B, and M.

As shown in Fig. 3(a), the UD-SJ has the best rectangular E-field distribution and therefore the highest BV when K_CIB = 1. However, for the charge imbalanced UD-SJ (CIB-UD-SJ) with K_CIB < 1, the E-field peak rises at the top of the N-pillar. On the contrary, the E-field peak of the CIB-UD-SJ with K_CIB > 1 rises at the bottom of P-pillar. The E-field distribution is inclined, resulting in an approximate triangular E-field rather than rectangular E-field in the drift region.

As shown in Fig. 3(b), the E-field of VVD-SJ with a > 0 and b < 0 is higher in the middle and relatively lower at the two ends of the pillars when K_CIB = 1. Since the effect of charge imbalance is to raise the E-field at the two ends of pillars, the tilt degree of E-field in the drift region is weakened whether K_CIB < 1 and K_CIB > 1, compared with UD-SJ. Therefore, the degradation of BV under charge imbalanced condition is also reduced. Conversely, as shown in Fig. 3(c), for the VVD-SJ with a < 0 and b > 0, its E-field is lower in the middle and higher at the two ends of the pillars when K_CIB = 1, so the E-field of the drift region tilts more sharply whether K_CIB < 1 or K_CIB > 1. Therefore, the degradation of BV under charge imbalanced condition is more severe.

Based on the above analyses, increasing the E-field in the middle of drift region and decreasing the E-field at the two ends of the pillars when K_CIB = 1 is an effective way to expand W_BV. Although it will result in a drop in BV_max, a compromise between BV_max and W_BV can be achieved with appropriate values of a and b.

The doping profile of P/N pillars also affects R_on,sp of VVD-SJ. As shown in Fig. 4, the R_on,sp increases with K_CIB for both UD-SJ and VVD-SJ. Here, the R_on,sp window (W_Ron) is defined as the range of K_CIB when R_on,sp has ±2% changes from R_on,sp at K_CIB = 1 (R_on,CB ). Both UD-SJ and VVD-SJ almost have the same W_Ron of [0.6, 1.5]. It can be observed that changes of |a| doesn’t affect R_on,sp, as only the doping profile of the N-pillar influences the resistivity along the current path. VVD-SJ R_on,sp is predominantly determined by the drift region resistance (R_drift), which can be divided into three components, equivalent to three resistors connected in series:

1Rdrift=l29qμnQN⋅(11+b+1+11−b).

Here q and μ_n are electron charge quantity and mobility, respectively.

It is evident that R_drift is a monotonically increasing function of b within the interval (0, 1). Although R_on,sp increases with |b|, the change is minimal. The increment of R_on,CB of VVD-SJ relative to UD-SJ is only 2.4% when |a| = |b| = 0.2.

Beyond process tolerance for static characteristics, process tolerance for reliability is also crucial for SJ-MOS devices. Avalanche energy, defined as the maximum energy a power MOSFET can endure during an unclamped inductive switching (UIS) event, serves as a crucial metric for assessing the reliability of such devices^[15−19]. Fig. 5 illustrates the UIS circuit and parameters utilized in both simulation and experiment. The device under test (DUT) is the SJ-MOS. Initially, the applied gate voltage turns on the DUT, causing the inductance to charge. After a period of time, the gate voltage is reduced to zero, forcing the DUT into an avalanche state where it must endure both high voltage and high current simultaneously, as the energy stored in the inductor cannot change instantaneously. Considering that the UIS process is strongly related to the thermal effect, thermal resistance is added to the drain electrode of DUT to simulate the heat dissipation process from chip to package. The drain current of the DUT during UIS process can be increased by increasing t_on. I_AS is defined as the maximum avalanche current that makes the DUT just fail, and the maximum avalanche energy (E_AS) can be obtained by

2EAS=12L⋅IAS2.

Fig. 6 shows the typical voltage and current waveforms of the failure VVD-SJ. In simulation, the failure criterion of DUT is that its maximum lattice temperature (T_max) reaches the intrinsic temperature of silicon. Here T_max is set as 566 K according to the equation^[16]:

3Tmax=0.5EgklnND10NcNv.

Since the avalanche tolerance is related to E_AS, the relationship between E_AS and K_CIB is provided in Fig. 7. It can be observed that E_AS initially increases and then decreases as K_CIB rises, for both UD-SJ and VVD-SJ. Notably, the peak of avalanche energy does not correspond to the position of BV_max, but is instead located in the region where K_CIB > 1. This occurs because the avalanche current path shifts with changes in the E-field distribution, resulting to a corresponding alteration in the heat distribution.

As shown in Fig. 8 and Fig. 9, for both UD-SJ and VVD-SJ, when K_CIB≪ 1, meaning Q_P≪Q_N, the E-field peak is located at the top of the N-pillar. As a result, the SJ-MOS will break down at this position at a lower voltage, causing the avalanche current and heat to concentrate at the top of the device. The parasitic bipolar junction transistor (BJT), formed by the N+ source, p-body, and N-pillar, is prone to turning on, leading to a reduced E_AS^[20].

In addition, heat accumulation on the surface of SJ-MOS leads to a longer heat dissipation path. Thus, the temperature rise of the device is more serious. The positive feedback between temperature and current aggravates the failure of the device. With the increase of K_CIB, the position of E-field peak shifts downward along the pillars. Correspondingly, the breakdown point gradually moves to the middle of the pillars. An increasing number of holes generated during avalanche breakdown pass through the P-pillar to the source electrode, rather than the P-body region. Due to the increasing difficulty in triggering parasitic BJT conduction and the shortening of the heat dissipation path, E_AS rises rapidly. When Q_P = Q_N, most of the avalanche current flows through the pillars rather than the P-body, causing the rate of increase in E_AS due to the downward shift of the current to gradually slow. After E_AS reaches its maximum value, the continuous increase in Q_P causes the E-field at the bottom of the P-pillar to rise sharply, leading to a significant reduction in BV. This results in an extreme concentration of avalanche current and an unbalanced heat distribution, causing E_AS to drop.

The avalanche tolerance window (W_AV) is defined as the range of K_CIB over which E_AS decreases by 4% from its peak (E_AS,max). As shown in Fig. 7, the VVD-SJ with a > 0 and b < 0 exhibits a higher E_AS,max and a more gradual decline compared to the VVD-SJ with a < 0 and b > 0. For both UD-SJ and VVD-SJ, E_AS decreases by less than 4% from E_AS,max on the right side (where K_CIB > 1), even at K_CIB = 1.5. Therefore, the discussion will focus on the left avalanche tolerance window (W_LAV) where K_CIB ≤ 1. For UD-SJ, the E_AS,max and W_LAV are 184.2 mJ and [0.88, 1.00], respectively. For the VVD-SJ with a = 0.2 and b = −0.2, the E_AS,max and W_LAV are 184.1 mJ and [0.85, 1.00], respectively. Its W_LAV increases by 40.0% whereas E_AS,max is almost unchanged.

This can also be explained by the change in the avalanche current path and heat distribution. Compared with the UD-SJ, the current crowding at the two ends is reduced in the VVD-SJ with a > 0 and b < 0, as shown in Fig. 8(b), due to the enhanced E-field peak in the middle. Consequently, the high-temperature region becomes more concentrated in the middle of the device, resulting in a more uniform temperature distribution, as shown in Fig. 9(b). Conversely, due to the increased susceptibility of the E-field distribution in the VVD-SJ with a < 0 and b > 0 tilting in charge-imbalanced states, current is more likely to concentrate at the top and bottom of the device, as shown in Fig. 8(c). The high-temperature region is thus more concentrated at both ends of the device.

In conclusion, compared with UD-SJ, the VVD-SJ with a > 0 and b < 0 exhibits improved W_BV and W_AV, with only a slight reduction in BV_max and R_on,sp. To assess the trade-off between static characteristics and reliability, a comprehensive process window (W_C) is defined as the region where W_BV and W_AV overlap, as shown in Fig. 10. Notably, the center point of W_C (P_C) is located in the region of K_CIB > 1, rather than at the charge balance point. For the UD-SJ, its W_C and P_C are [0.88, 1.17] and 1.025, respectively.

Based on the principle of that impurity concentration of P-pillar gradually decreases, while the impurity concentration of N-pillar gradually increases along the pillars from the top, the VVD-SJ with a = 0.2 and b = −0.2 demonstrates an improved W_C. As shown in Fig. 10(b), W_C and P_C of the optimized VVD-SJ are [0.85, 1.24] and 1.045, respectively. The W_C expands by 34.48%.

The UD-SJ and the optimized VVD-SJ, designed with parameters consistent with the aforementioned simulations, have been fabricated for comparative verification. Fig. 11 shows the SEM images of the fabricated devices. The BV and E_AS curves obtained from the test are shown in Fig. 12.

Apart from differences caused by actual manufacturing process and limitation of implant conditions, the measured curves show good agreement with the simulation. For UD-SJ, its W_C and P_C are [0.985, 1.063] and 1.024, respectively. While W_C and P_C of the optimized VVD-SJ are [0.975, 1.081] and 1.028, respectively. W_C of VVD-SJ expands 35.90 % compared with that of the UD-SJ.

By adjusting the doping distribution in P/N pillars of SJ-MOS, the E-field distribution under charge imbalance conditions can be optimized, thereby expanding the device’s process window. It has been demonstrated that an optimal trade-off between breakdown voltage, avalanche tolerance, and process window can be achieved by increasing the P-pillar concentration at the top and decreasing it at the bottom, while doing the opposite for the N-pillar, and ensuring the total impurity of P column slightly higher than that of N column, which provides meaningful reference to the design and fabrication of SJ-MOS.