Journal of Semiconductors, Volume. 41, Issue 10, 102105(2020)

Design, modelling, and simulation of a floating gate transistor with a novel security feature

H. Zandipour1 and M. Madani2
Author Affiliations
  • 1Department of Physics, Georgia Southern University, Savannah, GA 31419, USA
  • 2Department of Electrical Engineering, University of Louisiana at Lafayette, Lafayette, LA 70504, USA
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    References(17)

    [1] O Fujita, Y Amemiya. A floating-gate analog memory device for neural networks. IEEE Trans Electron Devices, 40, 2029(1993).

    [2] G Wang, X Liu, W Wang. Solution processed organic transistor nonvolatile memory with a floating-gate of carbon nanotubes. IEEE Electron Device Lett, 39, 111(2018).

    [3] X Jia, P Feng, S Zhang et al. An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags. J Semicond, 34, 085004(2013).

    [4] J Lee, Y Jeong, H Jeong et al. Fabrication and characterization of a new EEPROM cell with spacer select transistor. IEEE Electron Device Lett, 26, 569(2005).

    [5] L Fang, W Kong, J Gu et al. A novel symmetrical split-gate structure for 2-bit per cell flash memory. J Semicond, 35, 074008(2014).

    [6] P Cacharelis, E Fong, E Torgerson et al. A single transistor electrically alterable cell. IEEE Electron Device Lett, 6, 519(1985).

    [7] D Dimaria, K Demeyer, D Dong. Electrically-alterable memory using a dual electron injector structure. IEEE Electron Device Lett, 1, 179(1980).

    [8] J Wu, L Q Zhang, Y Yao et al. Investigation of dynamic threshold voltage behavior in semi-floating gate transistor for normally-off AlGaN/GaN HEMT. IEEE J Electron Devices Soc, 5, 117(2017).

    [9] Y M Kim, S J Kim, J S Lee. Organic-transistor-based nano-floating-gate memory devices having multistack charge-trapping layers. IEEE Electron Device Lett, 31, 503(2010).

    [10] H Schauer, L V Tran, L Smith. A high-density, high-performance EEPROM cell. IEEE Trans Electron Devices, 29, 1178(1982).

    [11] A Kolodny, S Nieh, B Eitan et al. Analysis and modeling of floating-gate EEPROM cells. IEEE Trans Electron Devices, 33, 835(1986).

    [12] M Holler, M Guizar-Sicairos, E H R Tsai et al. High-resolution non-destructive three-dimensional imaging of integrated circuits. Nature, 543, 402(2017).

    [13] S E Quadir, J Chen, D Forte et al. A survey on chip to system reverse engineering ACM. J Emerg Technol Comput Syst, 13, 1(2016).

    [14] A K Henning, T Hochwitz, J Slinkman et al. Two-dimensional surface dopant profiling in silicon using scanning Kelvin probe microscopy. J Appl Phys, 77, 1888(1995).

    [15] L Bidani, O Baharav, M Sinvani et al. Usage of laser timing probe for sensing of programmed charges in EEPROM devices. IEEE Trans Device Mater Reliab, 14, 304(2014).

    [16]

    [17] C Denardi, R Desplats, P Perdu et al. Descrambling and data reading techniques for flash-EEPROM memories. Application smart cards. Microelectron Reliab, 46, 1569(2006).

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    H. Zandipour, M. Madani. Design, modelling, and simulation of a floating gate transistor with a novel security feature[J]. Journal of Semiconductors, 2020, 41(10): 102105

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    Paper Information

    Category: Articles

    Received: Mar. 2, 2020

    Accepted: --

    Published Online: Sep. 10, 2021

    The Author Email:

    DOI:10.1088/1674-4926/41/10/102105

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