Acta Physica Sinica, Volume. 69, Issue 5, 057101-1(2020)

A channel thermal noise model of nanoscaled metal-oxide-semiconductor field-effect transistor

Meng Zhang, Ruo-He Yao*, and Yu-Rong Liu
Author Affiliations
  • School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China
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    Figures & Tables(5)
    Structure diagram of the NMOS device.
    Schematic of the transistor with a fictitious dc source placed at point y = y1 in the channel.
    The channel thermal noise at different gate-source bias: (a) Comparison with the model only considering the channel length modulation effect; (b) comparison with the model using the existing temperature model.
    The channel thermal noise at different gate-source bias (Leff = 0.13 μm).
    • Table 1.

      Parameters of NMOS.

      NMOS的器件参数

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      Table 1.

      Parameters of NMOS.

      NMOS的器件参数

      参数数值
      vsat/m·s–11.0 ×105
      σ0.02
      tox/nm 1
      θ/V–11.058
      εSi/F·cm–111.7 × (8.85 × 10–14)
      εox/F·cm–13.9 × (8.85 × 10–14)
      λ5.23
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    Meng Zhang, Ruo-He Yao, Yu-Rong Liu. A channel thermal noise model of nanoscaled metal-oxide-semiconductor field-effect transistor[J]. Acta Physica Sinica, 2020, 69(5): 057101-1

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    Paper Information

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    Received: Oct. 7, 2019

    Accepted: --

    Published Online: Nov. 18, 2020

    The Author Email:

    DOI:10.7498/aps.69.20191512

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