Microprocessors, Volume. , Issue 3, 39(2025)

Design and Optimization for High Voltage SOI LDMOS Device

QU Hanbin1,2, ZHAO Yongrui1,2, SHI Xiang1,2, TANG Xiaolong3, WEN Hengjuan4, CHEN Chen3, and ZHUO Xin3
Author Affiliations
  • 1North-China Integrated Circuit Crop. Ltd., Shijiazhuang 050051, China
  • 2The 13th Research Institute, CETC, Shijiazhuang 050051, China
  • 3School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 61731, China
  • 4Beijing Zhenxing Institute of Metrology and Measurement 100074, China
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    References(15)

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    [2] [2] OKAWA T, EGUCHI H, TAKI M, et al. 2000 V SOI LDMOS with new drift structure for HVICs[C]. 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, Prague, Czech Republic, 2016:435-438.

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    [5] [5] LI Y, ZHU S, WU J, et al. Research for radiation-hardened high-voltage SOI LDMOS[J]. Journal of Semiconductors, 2019, 40(5): 41-45.

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    [8] [8] NOVOSELOV S A, GUSEV R M, MASAL’SKII V N. Temperature Dependencies of the Breakdown Voltage of a High-Voltage SOI LDMOS Transistor[J]. Russian Microelectronics, 2024, 53(5): 456-463.

    [10] [10] LI M,LIU A,YAO J, et al. Novel dynamic back-gate control technology for performance improvement in ultrathin double SOI LDMOS[J]. Journal of Power Electronics,2024: 1-10.

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    [15] [15] SHIMAMOTO S, YANAGIDA Y, SHIRAKAWA S, et al. High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology[C]. 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs. IEEE, San Diego CA,2011: 44-47.

    [17] [17] LIJUAN W,YE H,YUE S, et al. Novel High-K SOI LDMOS with;N;+;Buried Layer[J]. IETE Technical Review, 2022, 39(2): 310-315.

    [18] [18] LING D, YU F G, JUN Z, et al. 3-D analytical model of the high-voltage interconnection effect for SOI LDMOS[J]. Superlattices and Microstructures, 2021, 160.

    [19] [19] XIN Z, ZHIXUAN L, ZHANG Y Y, et al. Total-Ionizing-Dose Radiation-Induced Dual-Channel Leakage Current at Unclosed Edge Termination for High Voltage SOI LDMOS[J]. Ieee Transactions On Electron Devices,2021, 68(6): 2861-2866.

    [20] [20] ZHANG Y Y,MING Q,XIN J L, et al. Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68(4): 2064-2070.

    [21] [21] LEI S,QI T W,FU Y Z, et al. Effect of Drift Length on Shifts in 400V SOI LDMOS Breakdown Voltage due to TID[J]. IEEE Transactions on Nuclear Science, 2020,67(11): 1.

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    QU Hanbin, ZHAO Yongrui, SHI Xiang, TANG Xiaolong, WEN Hengjuan, CHEN Chen, ZHUO Xin. Design and Optimization for High Voltage SOI LDMOS Device[J]. Microprocessors, 2025, (3): 39

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    Paper Information

    Received: Nov. 14, 2024

    Accepted: Aug. 25, 2025

    Published Online: Aug. 25, 2025

    The Author Email:

    DOI:10.3969/j.issn.1002-2279.2025.03.007

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