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Microprocessors, Volume. , Issue 3, 39(2025)

Design and Optimization for High Voltage SOI LDMOS Device

QU Hanbin1,2, ZHAO Yongrui1,2, SHI Xiang1,2, TANG Xiaolong3, WEN Hengjuan4, CHEN Chen3, and ZHUO Xin3
Author Affiliations
  • 1North-China Integrated Circuit Crop. Ltd.， Shijiazhuang 050051， China
  • 2The 13th Research Institute, CETC, Shijiazhuang 050051, China
  • 3School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 61731, China
  • 4Beijing Zhenxing Institute of Metrology and Measurement 100074， China
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    QU Hanbin, ZHAO Yongrui, SHI Xiang, TANG Xiaolong, WEN Hengjuan, CHEN Chen, ZHUO Xin. Design and Optimization for High Voltage SOI LDMOS Device[J]. Microprocessors, 2025, (3): 39

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    Paper Information

    Received: Nov. 14, 2024

    Accepted: Aug. 25, 2025

    Published Online: Aug. 25, 2025

    The Author Email:

    DOI:10.3969/j.issn.1002-2279.2025.03.007

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