Chinese Optics, Volume. 17, Issue 3, 693(2024)

Design and application of CCD/EMCCD photoelectronic parameter test system

Ji SHEN1、*, VIACHESLAV V. Zabudsky2, Wei-jing CHANG1, Qi-yue NA1, Yun-fei JIAN1, OLEG V. Rikhalsky3, OLEKSANDR G. Golenkov2, and VOLODYMYR P. Reva2
Author Affiliations
  • 1East China Institute of Optoelectronic Integrated Devices, Suzhou 215263, China
  • 2V.E. Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv 01001, Ukraine
  • 3Bogomoletz Institute of Physiology of NAS of Ukraine, Kyiv 01001, Ukraine
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    Figures & Tables(14)
    Block diagram of the entire test system
    The block diagram of the direct and pulse voltage source unit
    Block diagram of the FPGA board
    Block diagram of the device (outlined by a dashed line) implemented in FPGA
    Amplification of DACs output voltages
    High voltage amplifier circuit
    Schematic diagram of the experimental driver on the base of GaN HEMT
    Driver’s power consumption and temperature at different output voltages and loads
    Flow chart for measuring maximum output voltage, charge capacity, and output amplifier responsivity
    Measuring results of test system. Volt-charge responsivity for normal and gain modes, average dark signal, and dependence of gain on R02HV voltage were measured
    • Table 1. Parameters of 16 DC channels

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      Table 1. Parameters of 16 DC channels

      ChannelquantitySetting range/VTotal relativeerrorNoise,mV/300 kHz
      1−5···+10typical: ±0.1%;maximal: ±0.5%from Vmax<0.15
      30···+15< 0.15
      4−5···+15< 0. 20
      40···+25< 0.40
      40···35< 0.70
    • Table 2. Parameters of 16 AC channels

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      Table 2. Parameters of 16 AC channels

      Channel quantitySetting range/ VWave front/ nsLoad (each channel)
      3HL, LL: –5...+10120..200up to 24 nF
      4HL: –5...+10 or 0...+15LL: –5...+10 or 0...+15< 15220 pF
      1HL: 0...+15LL: 0...+15< 15220 pF
      6HL: +5LL: 0< 5150 pF
      1HL: –5...+ 15;LL, ML: –5...+10(three level signal)120..200up to 24 nF
      1HL: –5...+45LL: –5...+ 45(square or sine wave)20100 pF
    • Table 3. Electrical parameters of EMCCD matrices measured by the test system

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      Table 3. Electrical parameters of EMCCD matrices measured by the test system

      NoParameterRange
      1Resistances between the pairs of chip contact pads
      2Average Dark Signal> 1 e/pixel/s
      3Dark Signal Non-uniformity (DSNU)
      4Multiplication Gain1~1000
      5Peak Output Voltage (POV)< 1 V
      6Output Amplifier Responsivity (OAR)μV/e-
      7Register Charge Handling
      8Electric Charge Transfer Efficiency (CTE)≤ 0.99995
    • Table 4. Measurements example of test system

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      Table 4. Measurements example of test system

      1.POV nm, norm mode (max) = 0.177 V;
      2.SC is (saturation charge) = 132151 e`/pixel;
      3.POV hgm, high gain mode (max) = 1.782 V;
      4.CHCgr, Charge Handling Capability of gain register = 1280481 e`/pixel;
      5.White column defects = 3
      6.Dark column defects quantity = 18
      7.Average Dark Signal (U) = 0.002939 V/pixel/s
      8.Average Dark Signal (e`) = 2396 e`/pixel/s
      9.OAR (output amplifier responsivity) = 1.416 uV/e` (NM: 1.226 uV/e`)
      10.Dark signal non-uniformity (DSNU) (rms) = 67.334 %
      11.Charge transfer efficiency (CTE) = 99.908 %
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    Ji SHEN, VIACHESLAV V. Zabudsky, Wei-jing CHANG, Qi-yue NA, Yun-fei JIAN, OLEG V. Rikhalsky, OLEKSANDR G. Golenkov, VOLODYMYR P. Reva. Design and application of CCD/EMCCD photoelectronic parameter test system[J]. Chinese Optics, 2024, 17(3): 693

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    Paper Information

    Category: Original Article

    Received: Jul. 4, 2023

    Accepted: Aug. 28, 2023

    Published Online: Jul. 31, 2024

    The Author Email: Ji SHEN (njustshenji@126.com)

    DOI:10.37188/CO.EN-2023-0016

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