CCD photo devices are one of the most widespread types of photodetectors. EMCCD, as a type of CCD, are highly sensitive instruments in the visible range, which have been successfully developed and used for observation in low light conditions and the registration of single photons in the last two decades^[1-8]. Many types of matrices that differ in resolution, information reading method, and choice of direct or backlight illumination have been designed for various applications. A wide range of CCD array photodetectors puts forward extensive and stringent requirements for the performance of measurement systems intended for sorting or characterizing those devices. There are a variety of papers about assembled camera testing and its driving circuits, but little information on measuring systems for non-testing chips on wafers or in packages^[9-14].

Those measuring systems should provide better options for simply adjusting constant and variable supply voltages. This is needed to develop the potential to define the operating mode of the chip, to develop the potential to test faulty chips so as to avoid damage to the measuring system, and to measure the variety of parameters for the chips under study. The invention of EMCCD matrixes has also led to the advancement of new requirements; specifically, an increased need for frequency, clock voltages, three-level pulse signals, and fine-tuning of phase overlaps.

Testing system with a certain degree of versatility and tuning capabilities is required to test the manufactured silicon chips, especially at the stage of setting the production technology. We develope a test system that allows automatic or manual operation of chips, measurement of crystal parameters on a wafer and in a package, and investigation of manufactured samples.

Fig. 1 presents a block diagram of the designed test system. The system consists of a personal computer with specially developed control software, a main box with output DIP-48 ZIF (zero insertion force) connector, a water-cooling subsystem, and temperature controller TED200C for EMCCD with embedded Peltier element and temperature sensor, KEITHLEY 2710 digital multimeter with two 7710 multiplexer cards and a commutation block for direct current (DC) parameter measurement, and an LED lighting system.

The main box contains a Direct and Pulse Voltage Source (DPVS-2), a Data Acquisition System (DAS) and an output DIP-48 ZIF (zero insertion force) connector. It is possible to plug different types of CCD into the ZIF connector on the main box using different adapters. The adapters incorporate a water-cycling cooling system with a copper heat sink plate mechanically connected to the CCD package’s back surface. TED200C temperature controller and Keithley 2701 multimeter were used to manage the chip's operating temperature with a built-in temperature sensor and Peltier element in approximately –20~+20°C range.

The sub-unit DPVS-2 in the main box is governed by the commands from the controlling program and provides all direct and pulse voltages used for CCD itself, the lighting system that exposes CCD, CDS (correlated double sampling), and analog to digital conversion (ADC) synchronization in the DAS sub-unit. CCD output signal is amplified and preprocessed by CDS, sampled by ADC, and transferred into the PC controlling program, which builds a picture and measures CCD parameters for given conditions.

The measuring part of the system consists of two 2-channel 14-bit ADCs with a sampling rate of up to 20 MHz. Analog and digital circuits of devices are galvanically isolated to minimize system noise. Each ADC channel has differential input, and the range of differential input signal equals ±1/2U_REF, where U_REF is the reference voltage that can be coded to 1 V or 2 V. The ADCs are plugged into the personal computer via a high-speed USB interface. The measured noise of ADC with shorted inputs was about 0.35 mV.

For CCD DC parameter measurement (short-circuits, leakages, output amplifier characteristics), the chip could be plugged into the main box using cable adapter 1 and a commutation block which contains current sensors and is the same as on the main box ZIF connector. Different types of CCD chips can also be investigated with the help of the corresponding adapter. It is possible to measure the parameters of CCD crystals on the wafer by connecting cable adapter 2 through the commutation block to the main box. DC parameters are investigated by sequentially applying a constant test voltage to individual pins of CCD and measuring currents for all other pins to ground. The voltage from current sensors is registered with the help of a digital multimeter Keithley 2710 with two multiplexer cards 7710 and transferred to the control program. This connection of CCDs in packages or on wafers also allows imaging at reduced clock frequencies.

This paper discusses each element of the system, its preliminary performance, and proposed improvements.

The designation of the DPVS-2 is supplying CCD by DC and Pulse voltages, clocking of CDS and ADC meter. Fig. 2 shows the block diagram of DPVS-2, which contains FPGA boards, a pulse stretcher board (16 channels), a buffer stage, three 16-channel boards of adjustable voltage regulators, a DDS (direct digital synthesis) sine shaping board (optional), up to 10 boards of adjustable pulse signal driver, and a high-voltage amplifier board.

As one can see on the DPVS-2 block diagram, the control commands come from the computer program over the LAN to the FPGA boards. They are the development board FPGA GigaBee XC6SLX (UM-TE0600) and the expansion board (UM-TE0603) from Trenz Electronic GmbH. Shown in Fig. 3 is the block diagram of the FPGA board that includes:

● Xilinx Spartan-6 XC6SLX100-2FGG484C FPGA

● 10/100/1000 GBit Ethernet transceiver (physical layer) Marvell Semiconductor 88E1111

● Two independent 16-bit-wide 1 GBit (128 MByte) DDR3 SDRAM in 2 banks

● 128 MBit (16 MByte) serial Flash memory with dual/quad SPI interface

● 48-bit node address chip Maxim Integrated Products DS2502-E48 (containing valid MAC address)

● Up to 52 differential FPGA input/output pins on B2B strips

● Up to 109 single-ended (+1 dual-purpose) FPGA input/output pins on B2B strips

● Ethernet (PHY), JTAG, and SPI pins on B2B strips

● Processor supervisory circuits with power-fail and watchdog Texas Instruments TPS3705-33

Fig. 4 shows the block diagram of the device (outlined by a dashed line) implemented in FPGA (on FPGA fabric) that contains soft microprocessor core MicroBlaze (designed for Xilinx FPGA), and peripheral blocks: DMA, FIFO, PLL, DDS, SPI, and Delay line.

Bank0 is used as processor RAM, and the microcontroller program loads there. The second memory bank (Bank1), DMA, FIFO, PLL, and delay line blocks together form the Digital pattern generator (DPG) (outlined by a dotted line). The microcontroller loads into Bank1 a computer-prepared timing diagram of charge transfer pulses, individualized for each type of EMCCD. MicroBlaze programs the DMA controller and PLL (pattern start and end addresses, output frequency). The implemented pattern generator can repeat fragments of a pattern a specified number of times (equivalent to a subroutine) and execute the entire pattern in a loop to save memory. On the START command, the DMA controller cycles through the memory area in Bank1 containing the corresponding pattern and writes these 16-bit words to the FIFO. From the FIFO, these words with a frequency specified by the PLL (88.88 MHz, 44.44 MHz, 22.22 MHz, 11.11 MHz) are fed to the individually for each bit PC-controlled delay lines (±4.5 ns).

It allows individual control signals of the charge transfer phases in CCD, ADC, and CDS clocking to be shifted with respect to the entire timing diagram. From the delay lines, 16 logic signals are fed to the FPGA output and through the expansion board to the next blocks.

In addition, the FPGA implements the Direct Digital Synthesis (DDS) unit (table sine waveform generation), which using an external 14-bit DAC (AD9744), allows the generation of a sinusoidal signal. One of the outputs of the delay lines synchronizes the DDS unit, allowing the phase of the sine wave to be adjusted within ±4.5 ns. FPGA implements an SPI block for controlling various devices via the SPI bus.

DPVS-2 contains three equivalent DVS-16 boards. Each board contains two 8-channel 12-bit AD5328 DACs controlled over the SPl interface opto-isolated from FPGA boards. The output voltages from the DACs are amplified by schematic identical amplifiers (Fig. 5). Their particular strength is that various supply voltages can be applied to the operational amplifier and the output transistor stage by switching the jumpers RJ3-RJ6, RJ9-RJ11. This makes it possible to obtain different ranges of output voltages for different channels. If the output voltage range of a specific channel is less than that of the operational amplifier, then use the RJ1 jumper instead of VT1. If a more extensive range of output voltages is necessary, use VT1 without jumper RJ1. This makes the range of output voltages from zero to the voltage limited by U_{ce_max} transistors attainable. Resistors R1, R2, and R9 set the offset and gain of each output amplifier.

Thus, there are 16 PC-controlled DC voltage sources on each board. The output voltage range is specified at build time. All channels are calibrated before use, and the calibration data is stored in the computer. Once calibrated, the voltages remain very stable for a long time.

One DVS-16 board is used to generate DC voltages to power the CCD and lighting system (LED power supply). The output voltages of this board’s channels are summarized in Table 1.

The other two boards are used to generate high and low pulse voltage levels and adjust sine amplitude and offset. High and low levels of DC voltages go to 10 CCD charge transfer phase driver boards. These drivers are EL7156 logic-level controlled analog switches that switch corresponding CCD pins between DC voltage sources, which set high or low pulse voltage levels. A part of the logic signals (formed in the DPG on the FPGA board) is used to control the switches. (The other part is used for clocking and synchronizing ADC and CDS.) These signals are fed to the analog switches through the analog pulse stretcher board and the buffer inverting stage. An analog pulse stretcher delays the decay of individual signals by a few nanoseconds (adjustable with a trimmer). This is necessary in order to adjust the overlap of charge transfer pulses of the pixels in CCD.

The pulse voltage forming method allows the production of any time diagram of control signals and the setting of their amplitude parameters with high accuracy (in the range V_p-p – 0÷15 V).

There is also one channel with three controllable states: low, mid, and high voltages. This may be useful, for instance, during the testing of interline transfer type CCDs.

The high voltage signal for the multiplication register is obtained by amplifying the output signal of one of the pulse voltage sources described above, or a sine wave shaper, by a high voltage amplifier.

Table 2 lists pulse voltage sources' output voltages and switching times at specific load capacitances.

Fig. 6 shows the high-voltage amplifier circuit. The high voltage amplifiers (50 V voltage swing) are made using a monolithic triple 5.5 ns CRT Driver LM2435T. The impulse output current of one amplifier channel can reach 0.2 A, which makes it possible to obtain rise and fall times about 25 ns at a load of 100 pF, $ \Delta U=50\;{\rm{V}} $ ($ \Delta t=\dfrac{C\;\Delta U}{I} $). Capacitor C10 can correct the amplifier's frequency response and compensate for the voltage surge when operating on a capacitive load. To reduce the rise/fall time, it is possible to combine the inputs and sum up the currents of several channels using a resistor adder. This requires IC selection with an output voltage difference between the channels of less than 0.6 V in the entire operating range. The amplitude characteristic of the amplifier is slightly non-linear and is corrected by software calibration at 32 points. Calibration data is stored in the computer. To further improve the accuracy of the high voltage setting, an automatic calibration procedure is available before measurements start.

Using a high-voltage amplifier to supply the multiplication register of EMCCD has several disadvantages: it consumes significant power (in comparison with resonant circuits), has low output voltage accuracy (compared to switches as in low-voltage pulse voltage sources described above), and oscillates at the edges of output pulses when the load capacitance changes, amongst other problems. Indeed, the average current consumed by a capacitive load without taking into account losses in an amplifier or switch can be expressed as $ \overline{I}=\Delta U\cdot C\cdot f. $ The average consumption current is about 50 mA, and the power consumption is about 2.5 W at typical conditions (C≈100 pF, ∆U≈50 V, f≈10 MHz).

In resonant circuits, energy flows from the inductor to the capacitor and back when the multiplication register capacitance of the EMCCD is included in the oscillating circuit. In this case, only the energy losses in the circuit elements have to be compensated. Naturally, the energy efficiency of such systems is much higher because losses are negligible.

The designed measuring system provides multi-functionality for investigative purposes. It operates at different frequencies (including DC), with various types of CCDs, with different adapters and cable adapters, with other load capacitance and diverse values of parasitic capacitances and inductances, which prevents the use of resonant circuits. Resonant power circuits are beneficial for end devices with EMCCDs (off-the-shelf cameras), where they operate at fixed frequencies in a fixed circuit with constant parasitic parameters.

The use of analog switches in the formation of rectangular pulses does not provide such a dramatic gain in energy efficiency, however, it allows for the achievement of better accuracy and stability of amplitude parameters compared to the use of high-voltage amplifiers for this purpose. Unfortunately, this paper’s authors do not know of any high-voltage fast analog switches used in integral design. Attempts to create such switches based on discrete elements (silicon MOSFETs) usually encounter a number of difficulties, especially at frequencies above 10 MHz, because of high switching losses, the Miller effect, large impulse currents when operating on a capacitive load, etc. The situation changed somewhat with the advent of GaN High Electron Mobility Transistors (HEMT) and specialized high-speed integrated circuits for half-bridge control on GaN transistors (for example, PE2910x Peregrine Semiconductor, etc.)^[15-16]. The use of these devices, which have a high switching speed and low on-state conduction loss, opens up a broad array of possibilities for creating high-voltage fast analog switches suitable for creating high-voltage AC sources for the EMCCD multiplication register. Our experiments in this area have shown the possibility of creating high-voltage switching power supplies with an output voltage of up to 50 V with switching times of ~5 ns at a load of up to 150 pF and operating frequencies of up to 15 MHz. The schematic diagram of the experimental driver is shown in Fig.7 and its power consumption results is shown in Fig. 8.

Table 3 lists parameters measurable by the developed system.

When rejecting crystals on a wafer or measuring chips in a case, the resistances between the buses are monitored first. The entire test of the DC parameter is divided into 2 parts: the measurements of currents at 0.25 V and at 5 V (if the previous test was successful). This is done to avoid big currents that may cause bus shortages that can lead to damage to the measuring bench. The scheme shown in Fig. 9 was used to determine maximum output voltage, charge capacity, output amplifier responsivity in normal and gain mode, and other electrical parameters. It is the scheme used when measuring chips without an antiblooming function. All current passes through a setting transistor RD. However, if the antiblooming function is embedded into the chip, the output signal dependence from RD-current is not applicable to defining output signal saturation. Instead, the dependence of output signal vs chip illumination is measured, and RD-current is measured at the saturation point.

Fig. 10 presents the results of tests for 640×512 EMCCD.

These graphs show volt-charge responsivity for normal and gain modes, average dark signal, and dependence of gain vs. R02HV voltage. The following EMCCD parameters are measured and calculated (Table 4).

The system’s main box includes the Direct and Pulse Voltage Source Two (DPVS-2) and Data Acquisition System (DAS). DPVS-2 generates the CCD-required DC bias and pulse driver signal. Especially for EMCCD, the high voltage gain uses an analog switch circuit based on GaN HEMT, which achieves high switching speed, low on-state conduction loss, flexible frequency control, and better accuracy and stability. The developed system enables the measurement of the photoelectrical parameters of various formats of CCD chips. The measuring system's construction principle allows it to be flexibly configured to study different types and formats of CCD matrixes. We examine the developed system to study the parameters of 576 × 288, 640 × 512, 768 × 576, 1024 × 1024, and 1280 × 1024 matrixes on the wafer as well in the package. The system allows automatic or manual rejection of crystals and measurement of chip parameters such as resistances between the pairs of chip contact pads, average dark signal, dark signal non-uniformity (DSNU), multiplication gain, peak output voltage (POV), output amplifier responsivity (OAR), register charge handling, electric charge transfer efficiency (CTE), etc.