Fig. 1. Device scaling development trends of indium phosphorus-based, silicon-based, and heterogeneous integrated optical circuits^[3]

Fig. 2. Block diagram of the whole process of SiPIC design and manufacturing

Fig. 3. Schematic diagram of the MPW design-delivery cycle

Fig. 4. Large-scale PIC optical and electrical IOs. Schematic diagrams of the structures (left), the layout modes (middle), and the alignment tolerance (right) of (a) the grating coupler^[41-42] and (b) the end coupler^[43-44]; (c) schematic diagrams of the three layout types of the electrical IO pad on the chip

Fig. 5. Transmission devices. (a) Effect of waveguide width and sidewall roughness on the total scattering loss of waveguide per unit length^[49]; (b) the relationship between the turning radius of a 90-degree waveguide and the turning loss, and the source of its loss composition^[50-51]; (c) cross-section of a silicon photonics process supporting 1-layer silicon waveguide, 2-layer silicon nitride waveguide, and 2-layer metal traces^[58]; (d) schematic diagram of the structure for multi-layer, cross-layer, and cross-transmission of optical signals, including multilayer wiring of silicon nitride-silicon waveguides, cross-layer coupling of silicon nitride-silicon nitride-silicon waveguides, and waveguide cross-transmission devices^[58-59]

Fig. 6. Schematics and layouts of IC and SiPIC devices. (a) Schematic diagram of a class of electrical devices and (b) the corresponding physical structure^[63]; (c) schematic diagram of a basic PIC and (d) the corresponding physical structure^[19]

Fig. 7. Structures of 1×2 MMI and Taper. (a) Schematic diagram of 1×2 MMI and the relationship between the structure size and additional insertion loss^[75]; (b) topography diagram of the scanning electron microscope (SEM) of the MMI obtained by actual processing, and the crosstalk intensity values of the directional coupler and MMI under different device lengths^[74-75]; (c) schematic diagram of key parameters of Taper and the relationship between Taper length and insertion loss under different designs^[79]; (d) schematic diagram of a double-layer etched Taper device for mode conversion, and the mode conversion efficiency under different structural lengths^[80]

Fig. 8. Optical filters. (a) AWG^[85]; (b) compact MRR^[87]; (c) cascaded MRRs^[86]; (d) cascaded MZI filters^[88]

Fig. 9. Thermo-optic phase shifter. (a) SEM cross-section and optical microscope characterization of MZI thermo-optic modulation device^[102]; (b) microscope characterization and SEM cross-section of MZI electro-optical modulation device^[103]; (c) schematic diagram, SEM characterization, and optical microscopy of multi-coiled heating arm structure^[104]

Fig. 10. Periodic slow-light structure for a small-footprint MZI electrical modulation device^[106]. (a) Optical microscopic characterization; (b) periodic structure SEM characterization

Fig. 11. Integrated light sources and photodetectors. (a) Left: a coupling structure from the light-emitting region of the Ⅲ-V waveguides to the silicon waveguide region; right: the relationship between the length of the coupling structure and the coupling efficiency at different tip widths of the Ⅲ-V waveguides^[111]; (b) schematic diagram of a basic photodetection coupling structure^[112]; (c) optical microscope image of a type of basic photodetector^[113]; (d) optical microscope image of a Ge photodetector with an echo wall structure^[114]

Fig. 12. Optical AI chip. (a) Schematic diagram of the implementation of an optical AI circuit using the Grid architecture^[45]; (b) the basic components of an optical AI circuit: light source (or optical IO), beam splitter, modulator, matrix calculation MZI, and photodetector^[122]; (c) optical microscope characterization of an optical AI chip, showing the actual footprint and layout of its basic components of the circuit^[122]; (d) block diagram of the implementation of multilayer neural network training using a single-layer network physical structure^[123]; (e) microscopic characterization of the optical coherent cell module and the basic constituent units, including a large number of modulation devices and metal wiring^[123]; (f) magnification of the optical microscope of the MZI thermo-optical modulation device based on directional coupler splitting^[123]

Fig. 13. Large-scale PIC chip design challenges. (a) Schematic diagram of the 1-dimensional distribution of the phase modulation unit and an example of its implementation in the basic optical phased array^[125]; (b) schematic diagram of the basic components and functional module layout of the optical phased array circuit^[124]; (c) challenges in the increasing size and design density of the PIC: (i) the phase modulator is distributed in two dimensions; (ii) metal trace density limitations; (iii) fan-in and fan-out complexity increase; (iv) the increasing difficulty of electrical I/O placement and wiring; (v) complex connection wiring within the chip

Fig. 14. Balance of SiPIC system performance and device integration number based on architecture optimization. (a) Schematic diagram of the photonic neural network architecture of the FFT unitary matrix^[45]; (b) schematic diagram of the arrayed phase control using row and column arrangement and coding power supply^[125]; (c) schematic diagram of the square increase in the number of components and the linear increase of side length in two-dimensional arrangement; (d) the layout of large array optical phased array and the effect of complex fan-out wiring

Fig. 15. Common defect types and device failure cases in IC chips^[134]. (a) SEM image of open circuit defects between long metal strips; (b) SEM characterization of void defects at the location of vias; (c) SEM image of through holes causing short circuits of left and right wires; (d) transmission electron microscope topography of grain distribution of 90 nm width copper wires^[135]; (e) CMOS inverter schematic (leakage caused by defects at the gate); (f) input and output voltage waveforms (top), full quiescent current waveform [when the current is reversed, the defective circuit generates a higher current than the normal circuit (bottom)]

Fig. 16. Processing consistency of TiN heaters. (a) Range of square resistance distribution of a TiN heater in the same chip; (b) the phase error caused by the application of a π phase-shift voltage based on the design value

Fig. 17. Processing consistency of optical devices. (a) Si line width is unevenly distributed on the 200 mm wafer after the etching step^[138]; (b) thickness distribution and discrete level of Si film layer within a batch and within each wafer^[138]; (c) SEM image of Si grating structure with rough sidewalls^[139]; (d) SEM image with a smooth edge structure treated with laser pulse exposure^[139]

Fig. 18. Influence of waveguide thickness and width on the n_eff of the transmitted optical signal^[138]. (a) Functional relationship and sensitivity analysis of the equivalent refractive index and width change of 220 nm thick waveguide at 1550 nm for TE0 mode; (b) functional relationship and sensitivity analysis of the equivalent refractive index and thickness change of 500 nm wide waveguide at 1550 nm for TE0 mode; (c) propagation loss spectrum of a 500 nm wide and 220 nm high single-mode waveguide, and inset is the insertion loss of the waveguide at 1550 nm at different lengths; (d) comparison of formant positions of 4 MZI devices from 3 different dies

Fig. 19. Consistency issues of mass production of SiPIC. (a) Schematic diagram of the hierarchy of consistency issues faced by mass production: batch-to-batch, wafer-to-wafer, intra-wafer, and design area; (b) common sources and monitoring methods for consistency issues within the design area and PCM and test structures; (c) schematic diagrams of common solutions to consistency problems in system design