Journal of Semiconductors, Volume. 41, Issue 11, 111407(2020)

Challenges and opportunities toward fully automated analog layout design

Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun, and David Z. Pan
Author Affiliations
  • Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin 78712, USA
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    References(94)

    [1] J Rijmenants, J B Litsios, T R Schwarz et al. ILAC: An automated layout tool for analog CMOS circuits. IEEE J Solid-State Circuits, 24, 417(1989).

    [2]

    [3] S Weaver, B Hershberg, U K Moon. Digitally synthesized stochastic flash ADC using only standard digital cells. IEEE Trans Circuits Syst I, 61, 84(2013).

    [4] A Fahmy, J Liu, T Kim et al. An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells. IEEE TCAS II, 62, 731(2015).

    [5]

    [6]

    [7]

    [8] M J Seo, Y J Roh, D J Chang et al. A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks. IEEE Trans Circuits Syst II, 65, 1904(2018).

    [9] S Weaver, B Hershberg, N Maghari et al. Domino-logic-based ADC for digital synthesis. IEEE Trans Circuits Syst II, 58, 744(2011).

    [10]

    [11]

    [12]

    [13] Y Park, D D Wentzloff. An all-digital 12 pJ/pulse IR-UWB transmitter synthesized from a standard cell library. IEEE J Solid-State Circuits, 46, 1147(2011).

    [14]

    [15]

    [16]

    [17]

    [18]

    [19] M Shim, S Jeong, P D Myers et al. Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J Solid-State Circuits, 52, 1077s(2017).

    [20]

    [21]

    [22]

    [23]

    [24]

    [25] R Castro-Lopez, O Guerra, E Roca et al. An integrated layout-synthesis approach for analog ICs. IEEE TCAD, 27, 1179(2008).

    [26]

    [27] M Ding, P Harpe, G Chen et al. A hybrid design automation tool for sar adcs in IoT. IEEE TVLSI, 26, 2853(2018).

    [28] C Wulff, T Ytterdal. A compiled 9-bit 20-MS/s 3.5-fJ/conv. step SAR ADC in 28-nm FDSOI for bluetooth low energy receivers. IEEE J Solid-State Circuits, 52, 1915(2017).

    [29]

    [30]

    [31]

    [32]

    [33] P Pan, C Chin, H Chen et al. A fast prototyping framework for analog layout migration with planar preservation. IEEE TCAD, 34, 1373(2015).

    [34] X Dong, L Zhang. Process-variation-aware rule-based optical proximity correction for analog layout migration. IEEE TCAD, 36, 1395(2017).

    [35]

    [36] L Zhang, N Jangkrajarng, S Bhattacharya et al. Parasitic-aware optimization and retargeting of analog layouts: A symbolic-template approach. IEEE TCAD, 27, 791(2008).

    [37]

    [38]

    [39]

    [40] J M Cohn, D J Garrod, R A Rutenbar et al. KOAN/ANAGRAM II: New tools for device-level analog placement and routing. IEEE J Solid-State Circuits, 26, 330(1991).

    [41]

    [42]

    [43]

    [44]

    [45]

    [46] F Balasa, S C Maruvada, K Krishnamoorthy. On the exploration of the solution space in analog placement with symmetry constraints. IEEE TCAD, 23, 177(2006).

    [47]

    [48]

    [49]

    [50]

    [51] P H Lin, Y W Chang, S C Lin. Analog placement based on symmetry-island formulation. IEEE TCAD, 28, 791(2009).

    [52]

    [53]

    [54]

    [55]

    [56] Q Ma, L Xiao, Y C Tam et al. Simultaneous handling of symmetry, common centroid, and general placement constraints. IEEE TCAD, 30, 85(2011).

    [57]

    [58]

    [59]

    [60]

    [61]

    [62]

    [63] P H Wu, M P H Lin, T C Chen et al. Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement. IEEE TCAD, 33, 879(2014).

    [64]

    [65] H C Ou, K H Tseng, J Y Liu et al. Layout-dependent effects-aware analytical analog placement. IEEE TCAD, 35, 1243(2016).

    [66]

    [67]

    [68]

    [69]

    [70]

    [71]

    [72] K Lampaert, G Gielen, W M Sansen. A performance-driven placement tool for analog integrated circuits. IEEE J Solid-State Circuits, 30, 773(1995).

    [73]

    [74]

    [75] U Choudhury, A Sangiovanni-Vincentelli. Constraint-based channel routing for analog and mixed analog/digital circuits. IEEE TCAD, 12, 497(1993).

    [76]

    [77] J W Lin, T Y Ho, I H R Jiang. Reliability-driven power/ground routing for analog ICs. ACM TODAES, 17, 1(2019).

    [78]

    [79]

    [80]

    [81]

    [82]

    [83]

    [84]

    [85] Q Hao, S Dong, S Chen et al. Constraints generation for analog circuits layout. International Conference on Communications, Circuits and Systems, 2, 1339(2004).

    [86] Z Zhou, S Dong, X Hong et al. Analog constraints extraction based on the signal flow analysis. International Conference on ASIC, 2, 825(2005).

    [87] P Wu, M P Lin, T Ho. Analog layout synthesis with knowledge mining. 2015 European Conference on Circuit Theory and Design (ECCTD), 1(2015).

    [88] M Eick, M Strasser, K Lu et al. Comprehensive generation of hierarchical placement rules for analog integrated circuits. IEEE TCAD, 30, 180(2011).

    [89]

    [90]

    [91]

    [92] H Chen, M Liu, B Xu et al. Magical: An open-source fully automated analog IC layout system from netlist to GDSII. IEEE Design & Test(2020).

    [93]

    [94]

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    Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun, David Z. Pan. Challenges and opportunities toward fully automated analog layout design[J]. Journal of Semiconductors, 2020, 41(11): 111407

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    Paper Information

    Category: Reviews

    Received: Jul. 18, 2020

    Accepted: --

    Published Online: Sep. 10, 2021

    The Author Email:

    DOI:10.1088/1674-4926/41/11/111407

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