Fig. 1. Increasing trend of AI model parameters quantity and computing power demand^[2]. (a) AI model parameters quantity; (b) AI computing power demand

Fig. 2. Development process of optoelectronic interconnection packaging technology^[8]

Fig. 3. Structure of COUPE technology^[30]

Fig. 4. Performance comparison of COUPE technology, 3D micro-bump with wire-bonding, and 3D micro-bump with TSV^[30].(a) Power consumption at different rates; (b) PDN impedance at different frequencies; (c) (d) insertion loss and reflection loss comparise at different frequencies

Fig. 5. Schematic diagram of CPO technology based on ceramic substrate^[31]

Fig. 6. Cross section of the FOWLP package^[32]. (a) Multi-mode fiber; (b) single-mode fiber; (c) optical transceiver module

Fig. 7. CPO based on glass substrate^[35]

Fig. 8. CPO based on silicon substrate^[14]

Fig. 9. Optical engine and switch in Marvell 2.5D package ^[21]. (a) Schematic diagram of 2.5D package scheme; (b) section view of 2.5D package; (c) optical engine in 2.5D package; (d) integrated switch with 16 2.5D packaged optical engine

Fig. 10. Optical transceiver based on silicon interposer^[43].(a) Section of 2.5D multi-chip photoelectric integrated package；（b）2.5D integrated optical transceiver

Fig. 11. CPO package scheme based on EMIB^[18]. (a) Schematic diagram of five optical IO chips connected to the FPGA through EMIB; (b) cross section view connected through EMIB; (c) EMIB cross-sectional view of embedded packaging substrate; (d) TeraPHY chip layout diagram

Fig. 12. CPO based on PIC with TSV^[44]. (a) Cross section of the 3D package; (b) schematic diagram of packaging scheme

Fig. 13. Broadcom 3D CPO schematic^[9]. (a) Cross section of the 3D package; (b) schematic diagram of packaging scheme

Fig. 14. Schematic illustration of optoelectronic module realized by cavity interposer^[45]. (a) Three-dimensional structure diagram of POeM; (b) schematic diagram of the overall package structure

Fig. 15. Major steps of TSV based on Si interposer^[41]