[1] [1] JIE L, TANG X Y, LIU J X, et al. An overview of noise-shaping SAR ADC: From fundamentals to the frontier[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 1: 149-161.

[2] [2] SHU Y S, KUO L T, LO T Y. An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(12): 2928-2940.

[3] [3] LIU J X, TANG X Y, ZHAO W D, et al. A 13-bit 0.005-mm2 40-MS/s SAR ADC with kT/C noise cancellation[J]. IEEE Journal of Solid-State Circuits, 2020, 55(12): 3260-3270.

[4] [4] YANG C S, QIU L, TANG K, et al. A 98.6 dB SNDR SAR ADC with a mismatch error shaping technique implemented with double sampling[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(3): 774-778

[5] [5] BAIRD R T, FIEZ T S. Linearity enhancement of multibit A/D and D/A converters using data weighted averaging[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995, 42(12): 753-762.

[6] [6] LIU J X, HSU C K, TANG X Y, et al. Error-feedback mismatch error shaping for high-resolution data converters[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(4): 1342-1354.

[7] [7] LIN Y Z, LIN C Y, TSOU S C, et al. 20.2 A 40MHz-BW 320MS/s passive noise-shaping SAR ADC with passive signal-residue summation in 14nm FinFET[C]//IEEE International Solid- State Circuits Conference. San Francisco, CA, USA. 2019: 330-332.

[8] [8] LIU J X, WANG X, GAO Z J, et al. 9.3 A 40kHz-BW 90dB-SNDR noise-shaping SAR with 4× passive gain and 2nd -order mismatch error shaping[C]//IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA. 2020: 158-160.

[9] [9] GUO W, ZHUANG H, SUN N. A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators[C]//Symposium on VLSI Circuits. Kyoto, Japan, 2017: C236-C237.

[10] [10] XIE T, WANG T H, LIU Z, et al. An 84-dB-SNDR low-OSR fourth-order noise-shaping SAR with an FIA-assisted EF-CRFF structure and noise-mitigated push-pull buffer-in-loop technique[J]. IEEE Journal of Solid-State Circuits, 2022, 57(12): 3804-3815.

[11] [11] WANG Z N, JIE L, KONG Z C, et al. A 150kHz-BW 15-ENOB incremental zoom ADC with skipped sampling and single buffer embedded noise-shaping SAR quantizer[C]//IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2023: 9-11.

[12] [12] CHENG K C, CHANG S J, CHEN C C, et al. A 94.3dB SNDR 184dB FoMs 4th-order noise-shaping SAR ADC with dynamic-amplifier-assisted cascaded integrator[C]//IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2024: 180-182.