Fig. 1. (Color online) Forecast of global data traffic and electricity in ICT^{[1, 2]}.

Fig. 2. (Color online) Three coupling modes of silicon-based III–V lasers: (a) lens coupling^[11], (b) edge coupling^[32], (c) evanescent coupling^[33].

Fig. 3. (Color online) Comparison of typical power–current characteristics of FP lasers. QD-LD (left) is insensitive to temperature and has an almost constant threshold current and slope efficiency. Other two pictures (right two) show the characteristics of two typical QW-LDs^[36].

Fig. 4. (a) TEM image of GaAs/Si interface generating a large number of dislocations^[43]. (b) The TDs density gradually decreased after DFLs^[24].

Fig. 5. (Color online) (a) Schematic and TEM images of interaction between QDs and TDs^[24]. (b) Room temperature PL spectra of InAs/GaAs QDs grown on GaAs and Si (001) substrates shows that PL peak intensity of QDs grown on Si (001) substrates is stronger, and the inset is an AFM image of a surface InAs/GaAs QDs 1 × 1 μm² grown on Si (001)^[47].

Fig. 6. (Color online) (a) Diagram of Ridge QD-LD reported by UCL university^[24]. (b) Schematic diagram of ring structure QD-LD, SEM top view and infrared imaging reported by UCSB University^[30].

Fig. 7. (Color online) Three types of silicon-based modulators: (a) PIN^[31], (b) PN^[59], (c) MOS^[63].

Fig. 8. (Color online) (a) Ridge waveguide PD designed by Intel Corp.^[66]. (b) Electrode-biased Ge waveguide PD by Kotura^[9]. (c) Ge PD was made by BiCMOS process, which increased the ratio of intrinsic region width to doped region width^[68].

Fig. 9. (Color online) (a) Device structures of 1 × 4 Ch optical (De)MUX with different waveguide width^[70]. (b) Microsoft image of fabricated 12 × 400 GHz MMI-AWG^[71].

Fig. 10. (Color online) (a) Image of athermal Si optical interposer with close-ups of the components. (b) 20 Gb/s eye diagram with continuous temperature change from 25 to 125 °C^[72].

Fig. 11. (Color online) (a) Photographs of the transmitter and receiver optical I/O core. (b) Cross section of the transmitter and receiver optical I/O core^[73].

Fig. 12. (Color online) Schematic structure of a 16-channel × 25 Gb/s silicon photonic optical transceiver on a package substrate. EIC and PIC are bonded together by solder bumps and mounted on a glass ceramic interposer (GCIP)^[76].

Fig. 13. (Color online) (a) EIC and (b) PIC photographs of a high-density 16-channel optical transceiver^[76].

Fig. 14. (Color online) This silicon interposer integrated the beam splitters to increase the number of interconnect channels^[57].

Fig. 15. (Color online) (a) Generic transceiver architecture of the N × 25 G Luxtera product. (b) Photograph of assembled 8 × 25 G chipset (without fiber array), including: EIC, LaMP and PIC^[11].

Fig. 16. Cross section of co-integrated optical and electronic structures on the chip^[78].

Fig. 17. (Color online) (a) Photograph of Sicoya’s EPIC transceiver^[78]. (b) Illustration of NMD modulator. Its mirrors are formed by two 1D-photonic crystals, and the p⁺, n⁺ doped areas are located in the nodes of the resonator standing wave^[78].

Fig. 18. (Color online) 8 channels of the Si MUX passband overlaid with the normalized output spectra of the CWDM8 transmitter^[82].

Fig. 19. (Color online) (a) Top view of demultiplexer, 16-ch AWG and Ge PD array. (b) Cross section of Ge PD^[13].

Fig. 20. (Color online) (a) Photograph of transceiver board with optical I/O and only two fibers are used in the fiber array during system test. (b) Tx transmission and filtered MLL spectra at 25 °C and 257 mA showing 8 RRMs aligned within the passband of the filter^[83].

Fig. 21. (Color online) (a) Two-bit optical DAC consisting of two EAMs. (b) Vector and eye diagram of the proposed topology optical PAM-4 generator^[84].

Fig. 22. (Color online) Pluggable QSFP28 module which combine 4 × 25 Gb/s channels into two 50 Gb/s PAM-4 streams^[92].

Fig. 23. (Color online) Block diagram of silicon photonic coherent PIC demonstrated by Acacia^[86].

Fig. 24. (Color online) (a) BER against required total laser power for coherent and IMDD systems. (b) Estimated ASIC power consumption for PAM4, CAP16, DMT and coherent schemes based on 5 nm CMOS^[96].