Fig. 1. (a) The schematic of the designed hybrid Si/LN MZM. (b) The cross-section of the hybrid Si/LN MZM showing different materials of the stack and their vertical dimensions.

Fig. 2. (a) Top view schematic and the optical mode transmission in the VAC. (b) The cross-section and the key dimensions of the VAC. (c) The insertion loss of the VAC as a function of Hgap and (d) Loverlap. (e) Influence of the alignment error on the loss of VACs.

Fig. 3. (a) Top view schematic of the 3 dB MMI splitter. (b) The simulated insertion loss of the designed MMI splitter. Inset: simulated mode propagation in the designed MMI splitter at 1550 nm.

Fig. 4. (a) Two-dimensional colormap plot of the VπL versus electrode spacing Wgap and etching depth Hrib and the schematic of the simulation mode. (b) The mode absorption loss induced by metal versus Wgap. (c) The optical mode field and the static electric field distribution in the single arm. Inset: the schematic of the single arm of the designed modulator. (d) VπL and Γmo versus thickness of the thin film silicon oxide Hox.

Fig. 5. (a) The finite element simulation values of α and (b) Zo versus Wsignal and Hmetal. (c) The Nm of this device versus frequency up to 200 GHz. (d) The calculated electro-optic response of silicon substrates with different resistivities.

Fig. 6. (a) The process flow of the proposed integrated SOI/LN modulator: (I) an 8 inch SOI wafer; (II) silicon patterning, oxide deposition, and CMP process; (III) direct bonding followed by ion-cut technology; (IV) LN waveguide formation and oxide deposition; (V) oxide windows opening and metal formation. (b) The SEM picture of the cross-section of Si and LN waveguides. (c) The top-down SEM picture of the local patterned metal. (d) The microscopic picture of the fabricated heterogeneous integrated SOI/LN modulator.

Fig. 7. (a) The flow of the direct bonding process based on ion-cut technology: (I) ion implantation in LN wafer; (II) wafer bonding of LN and SOI wafer; (III) annealing of the integrated wafer; (IV) CMP of LN film surface. (b) The measurement result of LN thin film after CMP. (c) The picture of this integrated SOI/LN wafer.

Fig. 8. (a) The experimental setup for the modulation measurement. (b) The triangle wave driving voltage and measured typical sinusoidal response of the modulated signals. (c) The corresponding VπL values under the triangular wave driving signals at different frequencies.

Fig. 9. (a) The experimental setup for the high-frequency-performance measurement. (b) The measured EO response of the modulator and the S11 parameters of the CPW electrodes.

Fig. 10. (a) The experimental setup for the eye diagram measurement. (b) The measured eye diagrams of the device with NRZ format from 36 Gbit/s to 96 Gbit/s and (c) PAM-4 format from 72 Gbit/s to 192 Gbit/s.

Fig. 11. Measured B2B BER curves versus the received optical power for NRZ signal at different rates.