AEROSPACE SHANGHAI, Volume. 42, Issue 4, 66(2025)

Research on 3D CT Non-destructive Testing Methods for Advanced Packaging of Microsystems

Lin DU1, Yan JIANG2, Zebin KONG1, Bo WANG1, Minwei ZHU1, Lanlai WANG1, and Kunshu WANG1、*
Author Affiliations
  • 1Shanghai Institute of Aerospace Technology and Basic Research,Shanghai201109,China
  • 2Shanghai Aerospace Control Technology Institute,Shanghai201109,China
  • show less
    References(37)

    [1] C L GAN, C Y HUANG. Advanced flip chip packaging, 67-94(2023).

    [2] S ZHANG, M NADERAN-TAHAN, M JAHRE et al. Balancing performance against cost and sustainability in multi-chip-module GPUs. IEEE Computer Architecture Letters, 22, 145-148(2023).

    [3] F SHEIKH, R NAGISETTY, T KARNIK et al. 2.5D and 3D heterogeneous integration:emerging applications. IEEE Solid-State Circuits Magazine, 13, 77-87(2021).

    [4] M F ABDULLAH, H W LEE. Technology review of CNTs TSV in 3D IC and 2.5D packaging:progress and challenges from an electrical viewpoint. Microelectronic Engineering, 290, 112189(2024).

    [5] J SUZANO, F ABOUZEID, G DI NATALE et al. On hardware security and trust for chiplet-based 2.5 D and 3D ICs:Challenges and Innovations. IEEE Access, 12, 29778-29794(2024).

    [6] M CAI, B LING, D CHEN et al. Double-layer-stacked silicon interposer for 2.5D packaging of 32×32 micromirror array chip. IEEE Transactions on Components,Packaging and Manufacturing Technology(2025).

    [7] C GE, X WANG, J DU et al. High-speed wafer-level TGV interposer for 2.5D CPO. Optics Communications, 131517(2025).

    [8] C CHOI, H KIM, J H KANG et al. Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence. Nature Electronics, 5, 386-393(2022).

    [9] F SUNNY, E TAHERI, M NIKDAST et al. Machine learning accelerators in 2.5 D chiplet platforms with silicon photonics, 1-6(2023).

    [10] E P LI, H MA, M AHMED et al. An electromagnetic perspective of artificial intelligence neuromorphic chips. Electromagnetic Science, 1, 1-18(2023).

    [11] H CAI, J YAN, S MA et al. Design,fabrication,and radio frequency property evaluation of a through-glass-via interposer for 2.5D radio frequency integration. Journal of Micromechanics and Microengineering, 29(2019).

    [12] C ZHI, G DONG, D YANG et al. Transmission channel and matching network design strategies in chiplet-based 2.5-D ICs for RF applications. IEEE Internet of Things Journal(2025).

    [13] T CHALOUN, S BRANDL, N AMBROSIUS et al. RF glass technology is going mainstream:review and future applications. IEEE Journal of Microwaves, 3, 783-799(2023).

    [14] K TOGASAKI, M MINAMI, D KANG et al. Development of packaging technology for 2.xD advanced packages;fine bump interconnection,fine Cu wiring and large package, 1-5(2024).

    [15] H KIM, J PARK, S LEE et al. Signal integrity analysis of through-silicon-via (TSV) with passive equalizer to separate return path and mitigate the inter-symbol interference (ISI) for next generation high bandwidth memory. IEEE Transactions on Components,Packaging and Manufacturing Technology, 13, 1973-1988(2023).

    [16] J ZHAO, Z CHEN, F QIN et al. Development of high performance 2.5D packaging using glass interposer with through glass vias. Journal of Materials Science:Materials in Electronics, 34, 1790(2023).

    [17] Y LAI, A TAKAHASHI, S PARK. Design guidelines for 2.5D packages featuring organic interposer with bridges embedded. IEEE Transactions on Components,Packaging and Manufacturing Technology(2024).

    [18] S F YANG, W C WANG. LIN Y T, 1098-1103(2024).

    [19] H KIM, J Y HWANG, S E KIM et al. Thermomechanical challenges of 2.5-D packaging:a review of warpage and interconnect reliability. IEEE Transactions on Components,Packaging and Manufacturing Technology, 13, 1624-1641(2023).

    [20] M A ALAM, M MAMUN. Electrical chip-package-board reliability of 2.5-D/3-D HI packaged systems:a perspective. IEEE Transactions on Electron Devices, 71, 7244-7255(2024).

    [21] K HIRANO, D KANG, M TAKAHASHI et al. Study of fabrication and reliability for 120 mm×120 mm extremely large advanced 2.5D package, 955-962(2024).

    [22] E SUHIR, S YI, J S HWANG et al. Elevated standoff heights of solder joint interconnections can result in appreciable stress and warpage relief. Journal of Microelectronics and Electronic Packaging, 16, 13-20(2019).

    [23] M Y TSAI, Y W WANG, C M LIU. Thermally-induced deformations and warpages of flip-chip and 2.5 D IC packages measured by strain gauges. Materials, 14, 3723(2021).

    [24] Y JIANG, Y CHEN, F HU et al. Solution to optimize warpage performance for 2.5 D fanout packaging, 1-4(2023).

    [28] X ZHANG, J H ZHU, J MA et al. Hardware security and reliability verification based on fault propagation model. Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 42, 92-97(2024).

    [29] J H LAU, M LI, D TIAN et al. Warpage and thermal characterization of fan-out wafer-level packaging. IEEE Transactions on Components, 7, 1729-1738(2017).

    [30] J W CHOI, L G ONG, H Y LI et al. Relationship between wafer-level warpage and Cu overburden thickness controlled by isotropic wet etching for through si vias. IEEE Transactions on Components, 3, 1820-1825(2013).

    [31] H C CHENG, L C TAI, Y C LIU. Theoretical and experimental investigation of warpage evolution of flip chip package on packaging during fabrication. Materials, 14, 4816(2021).

    [32] W SUN, W H ZHU, K S LE et al. Simulation study on the warpage behavior and board-level temperature cycling reliability of PoP potentially for high-speed memory packaging, 1-8(2008).

    [33] S WANG, Y SUN, C SHENG et al. Warpage analysis and prediction of the advanced fan-out technology based on process mechanics. IEEE Transactions on Components,Packaging and Manufacturing Technology, 11, 2201-2213(2021).

    [34] G SUN, S ZHANG. A review on warpage measurement metrologies for advanced electronic packaging. Microelectronics Reliability, 160, 115456(2024).

    [35] W K LOH, R KULTERMAN, H FU et al. Recent trends of package warpage and measurement metrologies, 89-93(2016).

    [36] M K SHIH, C HSU, Y CHANG et al. Warpage characterization of glass interposer package development, 1392-1397(2017).

    [37] J LAU, X FAN. Warpage management in semiconductor packaging. Hybrid Bonding,Advanced Substrates,Failure Mechanisms,and Thermal Management for Chiplets and Heterogeneous Integration, 261-321(2025).

    [38] C C LEE, C P CHANG, C Y CHEN et al. Warpage estimation and demonstration of panel-level fan-out packaging with Cu pillars applied on a highly integrated architecture. IEEE Transactions on Components,Packaging and Manufacturing Technology, 13, 560-569(2023).

    [39] C C LEE, C W WANG, C Y CHEN. Comparison of mechanical modeling to warpage estimation of RDL-first fan-out panel-level packaging. IEEE Transactions on Components,Packaging and Manufacturing Technology, 12, 1100-1108(2022).

    [40] M S M KHAN, C XI, M S U HAQUE et al. Exploring advanced packaging technologies for reverse engineering a system-in-package (sip). IEEE Transactions on Components,Packaging and Manufacturing Technology, 13, 1360-1370(2023).

    Tools

    Get Citation

    Copy Citation Text

    Lin DU, Yan JIANG, Zebin KONG, Bo WANG, Minwei ZHU, Lanlai WANG, Kunshu WANG. Research on 3D CT Non-destructive Testing Methods for Advanced Packaging of Microsystems[J]. AEROSPACE SHANGHAI, 2025, 42(4): 66

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category: Microsystems Devices and Reliable Applications

    Received: Jun. 9, 2025

    Accepted: --

    Published Online: Sep. 29, 2025

    The Author Email:

    DOI:10.19328/j.cnki.2096-8655.2025.04.007

    Topics