Fig. 1. Function block diagram of the latest generation chip based on the ZIF architectur^［5］

Fig. 2. Architecture of the traditional RF microsystem

Fig. 3. Architecture of the SRD RF microsystem

Fig. 4. Block diagram of the RF microsystem prototype

Fig. 5. RF microsystem in kind

Fig. 6. Packaging architecture for the traditional RF microsystem

Fig. 7. 3D packaging architecture for the SDR RF microsystem

Fig. 8. Division of the power plane inside the digital organic substrate

Fig. 9. Multilayer wiring inside the digital organic substrate

Fig. 10. S-parameter simulation of a key differential signal path on the digital substrate

Fig. 11. Simulation results of core voltage power supply on the digital substrate

Fig. 12. Traditional RF microsystem in kind

Fig. 13. Digital organic substrate in kind

Fig. 14. RF organic substrate in kind

Fig. 15. Ceramic packaging in kind

Fig. 16. RF microsystem in kind

Fig. 17. Integration process of the traditional RF microsystem

Fig. 18. Integration process of the new RF microsystem based on the ZIF architecture

Fig. 19. Architecture of the RFSoC

Fig. 20. Architecture of a new RF microsystem based on the RFSoC

Fig. 21. 3D architecture of the RF microsystem based on advanced packaging