Microelectronics, Volume. 54, Issue 2, 255(2024)
Progress on Embedded Bridge Packaging for Chiplet Integration
[1] [1] TIMOTHY M H, JEFFERT C D. Heterogeneous and 3D Integration at DARPA [C] // 2019 International 3D Systems Integration Conference. Sendai, Japan.2019: 1-4.
[2] [2] GARROP P. DARPA envisions CHIPS as new approach to chip design and manufacturing [EB/OL].(2018-10-17) [2023-01-12]. http://www.3dincites.com/2018/10/iftle-396-darpa-envisions-chips-as-newapproach-to-chip-design-and-manufacturing.
[5] [5] LAU J H. Recent advances and trends in advanced packaging [J]. Packaging and Manufacturing Technology, 2022, 12(2): 228-252.
[6] [6] LAU J H. Semiconductor advanced packaging [M].New York: Springer, 2021.
[7] [7] MADDEN L, WU E, KIM N, et al. Advancing high performance heterogeneous integration through die stacking [C ] // Solid-State Device Research Conference. Bardeaux, France. 2012: 18-24.
[8] [8] JIN Y, BARARATON X, YOON S W, et al. Next generation eWLB (embedded wafer level BGA)packaging [C] // Electronics Packaging Technology Conference. Singapore. 2010: 520-526.
[9] [9] TSENG C F, LIU C S, WU C H, et al. InFO (wafer level integrated fan-out)technology [C] // Electronic Components and Technology Conference. Las Vegas,NV, USA. 2016: 1-6.
[10] [10] ZHANG X, LIN J K, WICKRAMANAYAKA S, et al. Heterogeneous 2.5D integration on through silicon interposer [J]. Applied Physics Reviews, 2015, 2(2):021308.
[12] [12] RAVI M, SANDEEP S. Microelectronic package containing silicon patches for high density interconnects,and method of manufacturing same: US 8,064,224 B2 [P]. 2011-11-22.
[13] [13] BRAUNISCH H, ALEKSOV A, LOTZ S, et al.High-speed performance of silicon bridge die-to-die interconnects [C] // Electrical Performance Electronic Packaging and Systems. San Jose, CA, USA. 2011:95-98.
[14] [14] VISWANATH R, CHANDRASEKHAR A,SRINIVASAN S, et al. Heterogeneous SoC Integration with EMIB [C] // IEEE Electrical Design of Advanced Packaging and Systems Symposium.Chandigarh, India. 2019: 1-3.
[15] [15] DUAN G, KNAOKA Y, MCREE R, et al. Die Embedding Challenges for EMIB Advanced Packaging Technology [C] // IEEE 71st Electronic Components and Technology Conference. San Diego, CA, USA.2021: 1-7.
[16] [16] MAHAJAN R, SANKMAN R, PATLE N, et al.Embedded multi-die interconnect bridge (EMIB)—A high-density, high-bandwidth packaging interconnect[C] // Electronic Components and Technology Conference. Las Vegas, NV, USA. 2016: 557-565.
[17] [17] SIKKA K, BONAM R, LIU Y, et al. Direct bonded heterogeneous integration (DBHi) Si bridge [C] //IEEE 71st Electronic Components and Technology Conference. San Diego, CA, USA. 2021: 136-147.
[18] [18] LEE J, YONG G, JEONG M, et al. S-connect fanout interposer for next-gen heterogeneous integration[C] // IEEE 71st Electronic Components and Technology Conference. San Diego, CA, USA. 2021:96-100.
[19] [19] LIM S P, CHONG S C, SEIT W W, et al. Challenges and approaches of 2.5D high density flip chip interconnect on through mold interposer [C] // IEEE 20th Electronics Packaging Technology Conference.Singapore. 2018: 618-624.
[20] [20] CHONG C T, GUAN L T, HO D, et al.Heterogeneous integration with embedded fine interconnect [C] // IEEE 71st Electronic Components and Technology Conference. San Diego, CA, USA.2021: 2216-2221.
[21] [21] Highlights of the TSMC Technology Symposium-Part 2 [EB/OL]. (2020-09-07) [2023-01-12]. http://www. semiwiki.com/semiconductor-manufacturers/tsmc/290560-Highlights of the TSMC Technology Symposium-Part 2.
[22] [22] HSIUNG C and SUNDARRAJAN A. Methods and apparatus for wafer-level die bridge: US 10,651,126 B2 [P]. 2020-05-12.
[23] [23] LEE L, CHANG Y, HUANG S, et al. Advanced HDFO packaging solutions for chiplets integration in HPC application [C] // IEEE 71st Electronic Components and Technology Conference. San Diego,CA, USA. 2021: 8-13.
[24] [24] YOU J, LI J, HO D, et al. Electrical performances of fan-out embedded bridge [C] // IEEE 71st Electronic Components and Technology Conference. San Diego,CA, USA. 2021: 2030-2034.
[25] [25] LIN J, CHUNG C K, LIN C F, et al. Scalable chiplet package using fan-out embedded bridge [C] // IEEE 70th Electronic Components and Technology Conference. Orlando, FL, USA. 2020: 14-18.
[26] [26] LIU S L, KAO N, SHIH T, et al. Fan-out embedded bridge solution in HPC application [C] // IEEE 23rd Electronics Packaging Technology Conference.Singapore. 2021: 222-225.
Get Citation
Copy Citation Text
YUAN Yuan, ZHANG Zhimo, ZHU Yuan, MENG Dexi, LIU Shuli, WANG Gang. Progress on Embedded Bridge Packaging for Chiplet Integration[J]. Microelectronics, 2024, 54(2): 255
Category:
Received: Oct. 8, 2023
Accepted: --
Published Online: Aug. 21, 2024
The Author Email: