Semiconductor Optoelectronics, Volume. 46, Issue 2, 202(2025)

Design of a 60 Gb/s PAM4 Signal SerDes Receiver Based on Quarter-Rate Architecture

ZHANG Xuan, ZHANG Chunming, and SONG Yidi
Author Affiliations
  • Collega of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an 710100, CHN
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    References(12)

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    [2] [2] Zhang B, Vasani A, Sinha A, et al. 6.1 a 112 Gb/s serial link transceiver with 3-tap FFE and 18-tap DFE receiver for up to 43 dB insertion loss channel in 7 nm FinFET technology[C]//2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 5-7.

    [3] [3] Kim K, Yun D, Baek K, et al. A 48-Gb/s single-ended PAM-4 receiver with adaptive nonlinearity compensation[C]//2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023: 1-5.

    [4] [4] Wu X, Wang Z, Zhao Z, et al. A 20 Gbuad NRZ/PAM4 receiver frontend in 65 nm CMOS[C]//2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022: 1-3.

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    [8] [8] Wang H, Lee J. A 21-Gb/s 87-mW transceiver with FFE/DFE/analog equalizer in 65-nm CMOS technology[J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 909-920.

    [9] [9] Razavi B. The StrongARM latch [a circuit for all seasons][J]. IEEE Solid-State Circuits Magazine, 2015, 7(2): 12-17.

    [10] [10] Im J, Freitas D, Roldan A B, et al. A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET[J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3486-3502.

    [12] [12] Peng P J, Lee P L, Huang H E, et al. A 56-Gb/s PAM-4 transmitter/receiver chipset with nonlinear FFE for VCSEL-based optical links in 40-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2022, 57(10): 3025-3035.

    [13] [13] Wang D, Wang Z, Xu H, et al. A 56-Gbps PAM-4 wireline receiver with 4-tap direct DFE employing dynamic CML comparators in 65 nm CMOS[J]. IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2022, 69(3): 1027-1040.

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    ZHANG Xuan, ZHANG Chunming, SONG Yidi. Design of a 60 Gb/s PAM4 Signal SerDes Receiver Based on Quarter-Rate Architecture[J]. Semiconductor Optoelectronics, 2025, 46(2): 202

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    Paper Information

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    Received: Dec. 17, 2024

    Accepted: Sep. 18, 2025

    Published Online: Sep. 18, 2025

    The Author Email:

    DOI:10.16818/j.issn1001-5868.20241217001

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