With the continuous development of information technology, communication systems require high data transmission rates. To extend the high-frequency bandwidth and reduce the circuit power consumption simultaneously, we designed a 60 Gb/s PAM4 signal SerDes receiver for receiving quarter-rate architecture. A continuous time linear equalizer (CTLE) with transconductance trans-impedance amplifier (Gm-TIA) structure and a parallel four-tap feed forward equalizer (4-tap FFE) equalization strategy are proposed to extend the high-frequency bandwidth, and a quarter-rate structure is used to further reduce the circuit power consumption. The circuit is implemented based on a 28 nm CMOS process at 1.05 V/1.2 V supply voltage, and post-simulation results show that the CTLE compensates for 18.5 dB of channel fading at Nyquist's 15 GHz frequency, and after a 4-tap FFE eye width of 0.6 UI and an eye height of 120 mV, the overall receiver-side power consumption is 83.71 mW, with an energy efficiency of 1.40 pJ/bit. The proposed circuit has a core area of 394.55 μm × 343.53 μm and is suitable for high-speed serial interface and communication applications.