Microelectronics, Volume. 52, Issue 1, 6(2022)

FPGA Design and Implementation of a Large Integer Multiplier with High Speed Pipeline Structure

TU Zhenxing, WANG Xiaolei, DU Gaoming, and LI Zhenmin
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  • [in Chinese]
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    References(11)

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    [3] [3] WANG W, HUANG X M. FPGA implementation of a large-number multiplier for fully homomorphic encryption [C] // IEEE Int Symp Circ Syst. 2013: 2589-2592.

    [4] [4] XING X, HUANG X M, LING S, et al. FPGA design and implementation of large integer multiplier [J]. J Elec Inform Tech, 2019, 41(8): 1855-1860.

    [5] [5] HUANG X M, WANG W. A novel and efficient design for an RSA cryptosystem with a very large key size [J]. IEEE Trans Circ Syst Ⅱ: Expr Bri, 2015, 62(10): 972-976.

    [6] [6] YE J H, SHIEH M D. Low-complexity VLSI design of large integer multipliers for fully homomorphic encryption [J]. IEEE Trans VLSI Syst, 2018, 26(9): 1727-1736.

    [7] [7] WANG W, HUANG X M. VLSI design of a large-number multiplier for fully homomorphic encryption [J]. IEEE Trans VLSI Syst, 2014, 22(9): 1879-1887.

    [8] [8] ZHANG N, QIN Q, YUAN H, et al. NTTU: an area-efficient low-power NTT-uncoupled architecture for NTT-based multiplication [J]. IEEE Trans Comput, 2020, 69(4): 520-533.

    [9] [9] LUO H F, LIU Y J,SHIEH M D. Efficient memory-addressing algorithms for FFT processor design [J]. IEEE Trans VLSI Syst, 2015, 23(10): 2162-2172.

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    TU Zhenxing, WANG Xiaolei, DU Gaoming, LI Zhenmin. FPGA Design and Implementation of a Large Integer Multiplier with High Speed Pipeline Structure[J]. Microelectronics, 2022, 52(1): 6

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    Paper Information

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    Received: Mar. 10, 2021

    Accepted: --

    Published Online: Jun. 14, 2022

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210095

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