Microelectronics, Volume. 51, Issue 2, 270(2021)

Research on Key Electrical Parameters’ Testing Technology of 2.5D Silicon Interposer

LIU Yukui1, CUI Wei1,2, MAO Ruyan1, SUN Shi3, and YIN Wanjun1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    References(5)

    [1] [1] ZHANG G Q, VAN ROOSMLEN A J. More than Moore [M]. London: Springer, 2009: 3-5.

    [7] [7] GAMBINO J P, ADDERLY S A, KNICKERBOCKER J U. An overview of through-silicon-via technology and manufacturing challeges [J]. Microelec Engineer, 2015(135): 73-106.

    [8] [8] YOON K, KIM G, LEE W, et al. Modeling and analysis of coupling between TSVs metal, and RDL interconnects in TSV-based 3D IC with silicon interposer [C] ∥ 11th EPTC. Singapore. 2009: 702-706.

    [9] [9] LI J W, MA S L, LIU H, et al. Design, fabrication and characterization of TSV interposer integrated 3D capacitor for SIP application [C] ∥ IEEE 68th ECTC. San Diego, CA, USA. 2018: 1974-1980.

    [10] [10] LAU J H. Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration [J]. Int Symp APM. Xiamen, China. 2011: 462-488.

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    LIU Yukui, CUI Wei, MAO Ruyan, SUN Shi, YIN Wanjun. Research on Key Electrical Parameters’ Testing Technology of 2.5D Silicon Interposer[J]. Microelectronics, 2021, 51(2): 270

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    Paper Information

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    Received: Aug. 24, 2020

    Accepted: --

    Published Online: Mar. 11, 2022

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.200385

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