Researching | A 112 Gbps DSP-based PAM4 SerDes receiver with a wide band equalization tuning AFE in 7 nm FinFET

Journal of Semiconductors, Volume. 46, Issue 6, 062204(2025)

A 112 Gbps DSP-based PAM4 SerDes receiver with a wide band equalization tuning AFE in 7 nm FinFET

Huanan Guo^*, Yufeng Yao, Jiazhen Ni, and Xiang Gao

Author Affiliations

College of Integrated Circuits, Zhejiang University, Hangzhou 310058, China

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References(18)

[1] Y Krupnik, Y Perelman, I Levin et al. 112-Gb/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels. IEEE J Solid State Circuits, 55, 1077(2020).

[2] J Im, K Zheng, C A Chou et al. A 112-Gb/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR ADC and inverter-based RX analog front-end in 7-nm FinFET. IEEE J Solid State Circuits, 56, 7(2021).

[3] H Park, M Abdullatif, E Chen et al. A 4.63pJ/b 112Gb/s DSP-based PAM-4 transceiver for a large-scale switch in 5nm FinFET. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 5(2023).

[4] A Khairi, Y Krupnik, A Laufer et al. A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-based SerDes receiver with hybrid AFE capable of supporting long reach channels. IEEE J Solid State Circuits, 58, 8(2023).

[5] Z H Li, M Z Tang, T Y Fan et al. A 56-Gb/s PAM4 receiver analog front-end with fixed peaking frequency and bandwidth in 40-nm CMOS. IEEE Trans Circuits Syst II Express Briefs, 68, 3058(2021).

[6] S Parikh, T Kao, Y Hidaka et al. A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 28(2013).

[7] J Bailey, H Shakiba, E Nir et al. A 112-Gb/s PAM-4 low-power nine-tap sliding-block DFE in a 7-nm FinFET wireline receiver. IEEE J Solid State Circuits, 57, 32(2022).

[8] M Pisati, F De Bernardinis, P Pascale et al. A 243-mW 1.25–56-Gb/s continuous range PAM-4 42.5-dB IL ADC/DAC-based transceiver in 7-nm FinFET. IEEE J Solid State Circuits, 55, 6(2020).

[9] Y P Lin, P J Peng, C C Lu et al. 7.7 A 2.16pJ/b 112Gb/s PAM-4 transceiver with time-interleaved 2b/3b ADCs and unbalanced baud-rate CDR for XSR applications in 28nm CMOS. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 136(2024).

[10] B Y Ye, K Sheng, W X Gai et al. A 2. 29pJ/b 112Gb/s wireline transceiver with RX 4-tap FFE for medium-reach applications in 28nm CMOS, 118(2022).

[11] P W de Abreu Farias Neto, K Hearne, I Chlis et al. A 112–134-Gb/s PAM4 receiver using a 36-way dual-comparator TI-SAR ADC in 7-nm FinFET. IEEE Solid State Circuits Lett, 3, 138(2020).

[12] B Zand, M K Bichan, A Mahmoodi et al. A 1-58.125Gb/s, 5-33dB IL multi-protocol Ethernet-compliant analog PAM-4 receiver with 16 DFE taps in 10nm. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 1(2022).

[13] Z Guo, A Mostafa, A Elshazly et al. A 112.5Gb/s ADC-DSP-based PAM-4 long-reach transceiver with >50dB channel loss in 5nm FinFET. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 116(2022).

[14] E Depaoli, H Y Zhang, M Mazzini et al. A 64 gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS. IEEE J Solid State Circuits, 54, 6(2019).

[15] R J Tang, K N Wang, H F Sun et al. A 112-Gb/s PAM-4 receiver with ultra-fine gain adjustment CTLE and novel sample-and-reset slicer in 28-nm CMOS. 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 297(2024).

[16] M Harwood, N Warke, R Simpson et al. A 12.5Gb/s SerDes in 65nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery. 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 436(2007).

[17] D Menin, A Bandiziol, W Grollitsch et al. Design and simulation of a 12 gb/s transceiver with 8-tap FFE, offset-compensated samplers and fully adaptive 1-tap speculative/3-tap DFE and sampling phase for MIPI A-PHY applications. IEEE Trans Circuits Syst II Express Briefs, 67, 1369(2020).

[18] H D Lin, C Boecker, M Hossain et al. ADC-DSP-based 10-to-112-Gb/s multi-standard receiver in 7-nm FinFET. IEEE J Solid State Circuits, 56, 1265(2021).

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Huanan Guo, Yufeng Yao, Jiazhen Ni, Xiang Gao. A 112 Gbps DSP-based PAM4 SerDes receiver with a wide band equalization tuning AFE in 7 nm FinFET[J]. Journal of Semiconductors, 2025, 46(6): 062204

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Paper Information

Category: Research Articles

Received: Apr. 18, 2025

Accepted: --

Published Online: Jun. 30, 2025

The Author Email: Huanan Guo (HNGuo)

DOI:10.1088/1674-4926/25030001

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