With the rapid development of AI and machine learning in recent years, data centers experience an increasing demand for wider data transmission bandwidth. High-speed SerDes is the key technique to meet the throughput requirement. However, as data rates continue to rise, severe channel loss has become a significant obstacle to the performance of high-speed SerDes. When high frequency signals are transmitted through a lossy channel, they experience substantial amplitude attenuation and waveform distortion which lead to ISI. Therefore, channel loss must be equalized by the receiver (RX) circuits, including the analog front-end (AFE), to achieve low bit error rate (BER) data recovery^[1−10]. Furthermore, since channel length and transmitter (TX) equalization may vary across different applications, the RX is required to provide flexible equalization strength^[11−15]. An AFE design with flexible equalization tuning is highly desired even in DSP-based RX designs, as it can relax the requirements on the ADC dynamic range and simplify digital equalization. In this paper, we present a 112 Gbps DSP based PAM4 SerDes receiver design with a wide band termination and a wide band equalization tuning AFE. The AFE provides isolated and smooth equalization gain tuning at different frequency ranges, the total equalization tuning covers a wide band from 1 GHz to Nyquist frequency and supports a maximum equalization gain tuning range from 0 to 17.5 dB at 27 GHz.

In a DSP-based SerDes receiver, the AFE output is sampled and converted into an n-bits digital signal by the ADC. The digitized signal is then processed by a digital FIR equalizer to recover the original data. In addition to the desired baseband signal, the AFE output also contains non-idealities including ISI, non-linear distortion and random noises, all of which will increase the system’s BER. Among these, linear ISI is the primary contributor to BER and originates from channel loss and reflections. Although digital equalizers can compensate for most ISI given enough number of taps in the FFE and DFE, they have several limitations. The first limitation is that extra power is required to handle long-tap ISI caused by reflection noise which bounces between near-end channel discontinuities. To mitigate this, a well-matched termination from DC to Nyquist frequency is needed to reduce return loss at the AFE input. Additionally, the feedthrough bandwidth of the termination is also required to be wide, as it directly influences the total transfer function of the AFE. The second limitation is that the non-linear responses of circuit generate noise from linear ISI. This non-linearity arises from AFE’s distortion and ADC sampling when the signal amplitude at the AFE output exceeds ADC input dynamic range. The generated non-linear noise cannot be compensated by the digital equalizer, and its power is related to the amplitude of ISI. Furthermore, to keep the peak amplitude of the AFE output within ADC dynamic range, the power of the desired baseband signal will be limited if the ISI is large. As a result, the AFE should compensate for as much ISI as possible to minimize non-linear noises and preserve voltage headroom for the signal. The third limitation is from digital equalizer’s self-adaptation algorithm which provide the coefficients of the FFE and DFE. A common coefficient adaptation algorithm is the least mean square (LMS) method, which uses the error between the FIR equalization result and the original data as a gradient step to update the FIR coefficients^{[16, 17]}. However, in the RX, the actual original data transmitted by TX is unknown, so the data acquired from the ADC slicer decision is used for estimation. This means that the AFE equalization, combined with the initial DFE/FFE coefficients of the digital equalizer, are required to provide a BER of less than 0.5 to ensure the correct convergence of the self-adaptation algorithm. A shorter convergence time can be achieved if less ISI is present at AFE output initially. In conclusion, to address the limitations mentioned above, the AFE should provide necessary pre-ADC equalization and reduce the ISI.

The architecture of the proposed DSP-based RX is illustrated in Fig. 1. It consists of a wide band equalization tuning AFE, a SAR-ADC, a Mueller−Muller CDR and a DSP with digital FIR equalizer and CDR algorithm. As shown in Fig. 2, the AFE comprises a T-coil based input termination and two stages of trans-conductance (TAS) cascading with trans-impedance (TIS) continuous time linear equalizer (CTLE). Following the AFE, a SAR-ADC digitizes the data. The ADC has 32-way time-interleaved 7-bit SAR architecture with a total sampling rate of 56 GS/s. The ADC clock is generated by a phase interpolator (PI)-based Mueller−Muller CDR, which interpolates the 4-phase 28 GHz clock from the PLL and produces the sampling clock with the appropriate phase. The DSP is implemented with 1-tap DFE and 30-tap FFE to cancel the remaining ISI after the AFE. To achieve flexible wide band equalization tuning in the AFE, three equalization techniques are implemented. First, a high-pass branch (HP) is added to the first TAS. The high pass branch provides the main zero-pole pair and covers the low-band (from 1 to 10 GHz) equalization. Each TAS stage incorporates a source degeneration (SD) structure to provide the second and third zero-pole pairs, covering the mid-band (7 to 24 GHz) equalization. The high-band (20 to 28 GHz) equalization is realized through inductive peaking (PK) in the TIS stages using inductive feedback. The transimpedance of the TIS stages exhibits a 2nd-order transfer function with sufficient Q factor to generate gain peaking around the Nyquist frequency. The tuning of equalization at different bands are isolated from each other, enabling the AFE’s equalization to be flexibly adjusted to better match the channel loss. Transfer functions with different equalization technique combinations and corresponding pulse responses are shown in Fig. 3. As illustrated, the channel significantly attenuates the pulse and introduces substantial ISI. By sequentially adding HP, SD and PK, the low-band, mid-band and high-band equalization gains are increased as described above. Additionally, as the equalization gain better matches the channel response, the ISI is reduced and the pulse amplitude is increased. The detailed AFE circuit design and tuning implementation are discussed in the following sections.

The input termination of the AFE must match the channel’s characteristic impedance Z₀ = R₀ over a wide bandwidth to minimize the reflections at the RX input. In a conventional T-coil configuration, as shown in Fig. 4(a), the ESD diode is connected to the input of the first TAS stage. The total parasitic capacitance of ESD (C_ESD) and TAS input (C_L) are both shunted at the middle node of the T-coil. When the T-coil parameters are designed to provide a resistive input impedance, the input network’s bandwidth of this configuration is limited by the 50-Ohm termination resistor (R_T) and the large C_ESD, which is 250 fF in our design. Although the T-coil can extend the bandwidth of the termination RC by 2.828, it remains challenging to achieve a bandwidth reaching the signal’s Nyquist frequency (ω_nyq), which is 28 GHz in this design. To address this challenge, we propose to separate the TAS input from the ESD and connect the TAS to the T-coil loading node together with R_T as shown in Fig. 4(b). This configuration leverages the all-pass characteristic of the balance bridged T-coil network to enhance the bandwidth while maintaining a low input return loss. To realize an all-pass T-coil network and eliminate the influence of C_ESD, the value of the two T-coil inductances (L₁, L₂), the mutual coefficient (k), and the bridged capacitance (C_B) should satisfy the equations given by:

1{L1=L2=L=(4ξ2+1)CESDR0216ξ2CB=CESD16ξ2,k=4ξ2−14ξ2+1,RT=R0,

where ξ is the desired damping factor of T-coil’s all-pass insertion loss (S₂₁). As shown in Fig. 4(c), the T-coil and ESD can be modeled as a two-port network whose characteristic impedance matches the channel impedance, and S₂₁ is an all-pass function given by:

2S21=b2a1=s2−2ξωns+ωn2s2+2ξωns+ωn2.

Here, the ξ is chosen to be 0.87 to achieve the minimum group delay across the bandwidth of interest as shown in Fig. 5. The total transfer function of the termination and return loss at the input can be expressed as:

3{H(s)=VoVs=S21ZoutZout+R0Γin=S212Zout−R0Zout+R0.

Since S21 is all-pass, the termination transfer function and input return loss are only affected by the loading impedance Z_out at the termination’s output node. An additional termination inductor L_T of 180 pH is added in series with R_T to compensate for the high frequency loss of Z_out caused by C_L (100 fF). The simulated S21 and S11 are shown in Fig. 6. As can be seen, the bandwidth of the termination is extended compared to the conventional T-coil termination while the input return loss remains lower than −10 dB.

The TAS stage design and its small signal model are shown in Figs. 7(a) and 7(b). The source degeneration structure of the TAS stage provides the primary equalization gain with a 1st-order zero/pole pair created by an RC degeneration network at the source node of the input MOS devices M1/M2. The effective transconductance of M1/M2 (G_mn) is attenuated by the degeneration impedance, so the zero frequency is determined by the RC corner frequency. At high frequency, G_mn approaches the intrinsic transconductance of M1/M2 (g_mn) and the pole frequency is given by g_mn/C_s where C_s is the degeneration capacitance. As shown in Fig. 7(c), the equalization gain tuning is realized by adjusting the value of C_s, which does not affect the DC gain of the TAS stage. This ensures that the output signal’s amplitude is not reduced when increasing the equalization gain. The tunable source capacitance is implemented using a switched capacitor controlled by a 5-bit code. As the code increases, the value of C_s increases, pushing the zero/pole to a lower frequency. Although the ratio between zero and pole remains unchanged with C_s, the equalization gain decreases when the pole of SD approaches or even exceeds the parasitic secondary pole. The source degeneration structure also faces a challenge in covering the low frequency band, as it requires either a large R_s which reduces DC gain or a large C_s which occupies significant area. To address this trade-off between low-band equalization, circuit area and DC gain, a high-pass branch is added in parallel with the main branch. The feedthrough high-pass branch provides gain when its effective transconductance is comparable with the main branch. The high-pass filter resistance R_HF determines the pole frequency, while the ratio between high-pass filter capacitance C_HF and parasitic capacitance C_L determines the high-frequency gain. This structure enables the independent control of the low-band equalization corner frequency by tuning R_HF and the low-band equalization gain by tuning C_HF as shown in Fig. 7(d). Each of the low-band equalization tuning option is controlled by a 3-bit code. As the code increases, the value of R_HF and C_HF increase, pushing the equalization to a lower frequency with higher gain. For the 20 dB equalization gain, the R_HF is set to 400 Ohm and C_HF is set to 60 fF, while the loading capacitance C_L is approximately 80 fF. Notably, neither of these tuning mechanisms affects the main branch DC gain, allowing the R_HF to be designed with a large value to achieve low-frequency equalization without occupying excessive area. The outputs of the two branches are combined in the current domain by shunting the drain nodes of M1/M2 and M3/M4. The source degeneration structure, with source resistance R_s and capacitance C_s, is retained but focus on covering the mid-band equalization from 7 to 24 GHz. The values of R_s and transconductance of M1/M2 are designed to meet the desired DC gain and equalization gain, while C_s is tuned to control the mid-band equalization corner frequency. The total effective transconductance G_{m_total} of the TAS stage is given by:

4Gm_total=gmpsCHFRHF1+s(CHF+CL)RHF+gmn1+sCsRs1+gmnRs2+sCsRs,

where g_mp is the transconductance of M3/4. Thanks to the low-band equalization provided by the high-pass branch, the corner frequency of R_sC_s is set 4x higher than in the design using only source degeneration structure to provide low frequency zeros. This allows for a 2x reduction in both the size of C_s and the value of R_s, resulting a 6 dB increase in DC gain. For the 20 dB equalization gain, the R_s in both TAS stages are set to 80 Ohm and the C_s in the 1st and 2nd TAS stage are set to 250 and 100 fF correspondingly.

In TAS stage, higher equalization gain is achieved by sacrificing the low-frequency gain while maintaining high-frequency gain. As a result, the TIS stage should provide large enough transimpedance while maintaining a wide bandwidth to achieve an appropriate DC gain. Furthermore, at high frequency, the roll-off of channel loss is quite sharp. Instead of stacking 1st-order zeros near the Nyquist frequency to boost the equalization gain, inductive feedback TIS stages are implemented to overcome the trade-off between DC gain and bandwidth while driving the heavy loading from the ADC. To further enhance the high-band equalization gain from 20 to 28 GHz, shunt inductive peaking is exploited in the TIS feedback path as shown in Fig. 8(a). Its small signal model is illustrated in Fig. 8(b). As long as the open-loop gain of the TIA is much greater than 1, the trans-impedance Z_T of the TIS stage can be simplified to a 2nd-order transfer function:

5ZT=VoIin≈RfbCfbgms−1s2ωn2+sωnq+1,where{ωn2=gmRfb(CfbCi+CfbCo+CiCo)q=gmRfb(CfbCi+CfbCo+CiCo)gmRfbCfb+Ci+Co−gmLfbRfb,

where g_m is the total transconductance of TIA input device, R_fb is the feedback resistance, C_i is the input parasitic capacitance, C_o is the output loading capacitance, C_fb is the feedback parasitic capacitance and L_fb is the feedback inductance. This structure demonstrates the benefit that the nature frequency ω_n of Z_T surpass the intrinsic pole of R_fbC_o. To boost g_m and push ω_n even higher, M7/M8/M9/M10 can be scaled up. However, the effect of bandwidth enhancement diminishes when the transistor parasitics become significant compared to the loading capacitance C_o. To achieve high-band equalization gain, L_fb must be large enough to ensure a quality (Q) factor larger than 0.707. Therefore, L_fb is designed to be 200 pH with R_fb equals to 70 Ohm in both TIS stages. Due to the heavy output loading from the ADC, the overall peaking in this design is achieved by cascading the staggered peaking of the two TIS stages. The high-band equalization is then tuned using a switch capacitor at the output node by a 5-bit code. As the code increases, the value of loading capacitor C_o decreases, and both ω_n and Q factor increase, thereby boosting the equalization gain as shown in Fig. 8(c). The AFE’s total tuning options across all the bands are illustrated in Fig. 8(d).

To evaluate the performance of the AFE, the signal−noise-ratio (SNR) at the AFE output is commonly calculated^[18]. However, the noise components at AFE output come from different sources. The probability distribution of ISI depends on the waveform of the pulse response and the received data pattern, so it cannot be treated as random noise. Additionally, the ISI within FIR tap range will be mostly compensated by digital equalizer and thus will not directly affect the overall BER. On the other hand, the waveform distortion caused by non-linearity varies from symbol to symbol, making it difficult to quantify. In this analysis, we use the mean value of AFE output amplitude as the estimated signal amplitude because the expectation of ISI and random noise is zero. Furthermore, the ISI within the FIR tap range is excluded from noise power calculation and can be estimated based on the FIR coefficient convergence result. The impact of the excluded ISI is reflected in the reduction of signal power, as the maximum amplitude is limited by the ADC’s dynamic range. The remaining noise consists of the residual ISI, non-linearity-induced noise and random noise. By calculating the mean square value of the deviation between the sampling result and the estimated signal plus ISI, we can derive an estimated noise power which accounts for all noise components and has a form similar to the error function of LMS algorithm mentioned earlier. Fig. 9 illustrates the simulated signal power, noise power, SNR and symbol-error-rate (SER) calculated from SNR. A backplane channel model with 20 dB insertion loss is used for SNR simulation. As shown, increasing the control code of SD, HP and PK, which correspond to increasing the equalization gain, results in an increase in both the signal amplitude and SNR at AFE output, leading to a better SER estimation. Notably, the noise is not monotonic with respect to the equalization gain because the input random noise is amplified by equalization, while non-linearity-induced noise decreases as ISI is reduced.

The PAM4 receiver with the proposed AFE was fabricated in a 7 nm FinFET technology and the die micrograph is shown in Fig. 10. The AFE’s frequency response was measured by sending single tone signals from an off-chip sine-wave generator at different frequencies and read the detected signal level at the ADC output under different equalization configuration. The package and input trace are de-embedded to illustrate the AFE’s frequency response. The full equalization tuning range of the AFE reaches 17.5 dB at Nyquist frequency with 0 dB DC gain as shown in Fig. 11(a). Figs. 11(b) and 11(c) show the overall received PAM4 eye diagrams after digital FIR for 10.7 dB/29.6 dB channels by sweeping the PI controlling code and 8192 data are acquired under each PI code. The AFE equalization tuning is manually optimized for two channels. With 10.7 dB channel, an eye-height of 32 in 128 total codes and an eye-width of 0.33 UI are measured. When the channel loss increases to 29.6 dB, the eye-height decreases to 15 out of 128 codes with an eye-width of 0.29 UI. The BER is measured with a 112.5 Gb/s PRBS-31 pattern. A BER of 6 × 10⁻⁹ is achieved with 29.6 dB channel loss. The typical receiver power consumption is 352 mW with 65.5 mW from the AFE. Table 1 provides a performance comparison with prior PAM4 SerDes receivers.

This paper presents a 112 Gb/s SerDes receiver featuring a wide band equalization tuning AFE. The AFE combines equalization techniques including SD, HP, and PK. Each equalization technique provides independent equalization gain control across different frequency bands. Consequently, the proposed AFE enables compensation for various channel losses across frequencies from DC to Nyquist frequency. Thanks to AFE’s flexible wide band equalization tuning, the receiver achieves wide eye opening under both 10.7 and 29.6 dB channel loss and a BER of 6 × 10⁻⁹ is achieved under 29.6 dB channel loss with competitive power efficiency.