[1] [1] STEINBUCH M, OOMEN T, VERMEULEN H. Motion control, mechatronics design, and Moore's law[J]. IEEJ Journal of Industry Applications, 2022, 11(2): 245-255.

[2] [2] LI M. Review of advanced CMOS technology for post-Moore era[J]. Science China Physics, Mechanics and Astronomy, 2012, 55(12): 2316-2325.

[4] [4] PAARHUIS B, DE BOEIJ W, DESHPANDE A, et al. Extending DUV productivity and overlay through joint dry and immersion scanner advancements[C]//Optical Microlithography XXXIV. Online Only, USA. SPIE, 2021: 130-141.

[5] [5] ORJI N G, BADAROGLU M, BARNES B M, et al. Metrology for the next generation of semiconductor devices[J]. Nature Electronics, 2018, 1: 532-547.

[13] [13] CLAEYS C, CHIAPPE D, COLLAERT N, et al. Advanced semiconductor devices for future CMOS technologies[J]. ECS Meeting Abstracts, 2015, (20): 1326.

[14] [14] LIU A H, ZHANG X W, LIU Z Y, et al. The roadmap of 2D materials and devices toward chips[J]. Nano-Micro Letters, 2024, 16(1): 119.

[15] [15] SEGURA J. Integrated microelectromechanical systems in the More than Moore era[C]//2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS). Palma de Mallorca, Spain. IEEE, 2017: 1.

[16] [16] SALAH K. More than Moore and beyond CMOS: New interconnects schemes and new circuits architectures[C]//2017 IEEE 19th Electronics Packaging Technology Conference (EPTC). Singapore. IEEE, 2017: 1-6.

[24] [24] ARKET & TECHNOLOGY REPORT. Laser technologies for semiconductor manufacturing processes[EB/OL]. (2017-10-01)[2024-03-09]. https://medias.yolegroup.com/uploads/2017/10/Flyer-Laser-Technologies-for-Semiconductor-Manufacturing-.pdf.

[30] [30] LAU J H. Evolution and outlook of TSV and 3D IC/Si integration[C]//2010 12th Electronics Packaging Technology Conference. Singapore: IEEE, 2010: 560-570.

[32] [32] ANDRY P, BUDD R, POLASTRE R, et al. Advanced wafer bonding and laser debonding[C]//2014 IEEE 64th Electronic Components and Technology Conference (ECTC). Orlando, FL, USA. IEEE, 2014: 883-887.

[33] [33] UHRMANN T, POVAAY. Temporary carrier technologies for eWLB and RDL-first fan-out wafer-level packages[J]. Advances in Embedded and Fan-Out Wafer Level Packaging Technologies, 2019: 457-470.

[37] [37] WAY D W C, YING L. High speed wafer dicing with ablation laser cut[C]//2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT). Penang, Malaysia. IEEE, 2008: 1-3.

[38] [38] CERENO D I, WICKRAMANAYAKA S. Stealth dicing challenges for MEMS wafer applications[C]//2017 IEEE 67th Electronic Components and Technology Conference (ECTC). Orlando, FL, USA. IEEE, 2017: 358-363.

[40] [40] TSORMPATZOGLOU A, DIMITRIADIS C A, CLERC R, et al. Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[J]. IEEE Transactions on Electron Devices, 2007, 54(8): 1943-1952.

[43] [43] PANKRATOV E L. Optimization of laser annealing of radiation defects for production of an implanted-junction rectifier[J]. Journal of Physics D Applied Physics, 2009, 42(7): 079802.