Optics and Precision Engineering, Volume. 20, Issue 5, 1076(2012)

Manufacture of low-g micro inertial switch utilizing SOI with double buried layers

WANG Chao*, WU Jia-li, and CHEN Guang-yan
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  • [in Chinese]
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    A low-g micro inertial switch based on the planar rectangular helical spring was developed by utilizing a SOI (Silicon-On-Insulator) wafer with double buried layers and the manufacturing technology including KOH etching, Inductance Coupled Plasma (ICP) etching, anodic bonding and spray coating. Based on the self-stop technique for KOH etching and ICP etching of the buried layers, the precision of the spring thickness was controlled to be ±0.46 μm. The electrical property of the SOI wafer was analyzed. The anodic bonding between borosilicate glass and SOI wafer was successfully carried out utilizing the uniform electric potential technique,and an anti-stiction structure with a size about 200 μm×200 μm was fabricated using the maskless pyrex-etching in the process of wafer cleaning and drying. Finally, a silicon-base was used to solve the Au-Si eutectic problem resulted from high temperature during ICP etching process. Experiments show that the chip yield is greatly increased by optimizing the fabrication process and the fabrication process can support the production of low-g micro inertial switches in batches.

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    WANG Chao, WU Jia-li, CHEN Guang-yan. Manufacture of low-g micro inertial switch utilizing SOI with double buried layers[J]. Optics and Precision Engineering, 2012, 20(5): 1076

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    Paper Information

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    Received: Jan. 20, 2012

    Accepted: --

    Published Online: Aug. 8, 2012

    The Author Email: WANG Chao (wchao.lzms@gmail.com)

    DOI:10.3788/ope.20122005.1076

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