Fig. 1. Conventional FPM ADC architecture and operating waveforms

Fig. 2. Subthreshold comparator

Fig. 3. Integration reset process of the conventional FPM ADC

Fig. 4. Schematic diagram of the low-power high-linearity pixel-level ADC architecture

Fig. 5. Pre-comparator circuit

Fig. 6. Operating current comparison between standard inverter and starved inverter

Fig. 7. Relationship between delay time and bias voltage in starved inverters

Fig. 8. Comparator circuit in the proposed architecture

Fig. 9. Delay time and tail current characteristics of the comparator

Fig. 10. Timing diagram of the proposed architecture

Fig. 11. Photomicrograph of the pixel unit layout

Fig. 12. 2k×2k readout circuit layout

Fig. 13. Input-output linearity versus illumination intensity

Fig. 14. Power consumption versus illumination intensity

Fig. 15. ADC output results

Fig. 16. Comparison of the grayscale histogram of the original image with the grayscale distribution