In the field of infrared imaging technology, the digitization of infrared readout circuits has emerged as a significant research trend. Compared with traditional analog infrared focal plane arrays (FPAs), digital infrared FPAs demonstrate substantial advantages, including enhanced signal processing accuracy, superior anti-interference capability, and improved integration potential. Consequently, research on digital infrared FPAs has become a focal point, with the design and optimization of pixel-level infrared readout circuits constituting a central research focus. Currently, most digital infrared readout circuits employ a pulse-frequency modulation (PFM) architecture. This structure achieves signal digitization by modulating input signals into variations in pulse frequency. However, in the long-wave infrared (LWIR) band, where detectors generate relatively large equivalent photocurrents, the PFM architecture exhibits notable limitations in terms of power consumption and linearity. Specifically, under high-injection-current conditions, PFM-based circuits suffer from elevated power dissipation and susceptibility to nonlinearity between input and output signals, leading to signal distortion. This phenomenon is particularly pronounced in LWIR FPAs, ultimately constraining the performance enhancement of LWIR detectors.Currently, PFM ADC also faces two problems. The first problem is that increasing the maximum flip times of the counter and comparator within the integration time can enhance the dynamic range, but it will also consume more power. The second problem is that in existing works, subthreshold comparators are used to reduce power consumption, which increases the delay time of the comparator and reduces the linearity. In this paper, a low-power digital pre-comparator is introduced to achieve the precise interval working mechanism. At the same time, the delay time of the comparator is reduced by no longer limiting the bias current of the comparator during the comparison stage to achieve the goal of reducing the power consumption of the readout circuit and improving the linearity of the readout circuit.The method proposed in this paper is completely designed and simulated based on 55 nm CMOS technology. The experimental results show that: When the input voltage is 3.3 V and the typical light intensity is 20 nA, the overall power consumption of the pixel unit is only 0.65 μW, while the delay time of the comparator module is greatly reduced compared with the traditional structure, so that the input-output nonlinear error is only 0.105%, the charge processing capacity reaches 3.1 Ge^-, and the center distance of a single pixel is 20 μm, and the imaging results are shown (Fig.14). The structure proposed in this paper can restore the original image well.This paper presents an improved PFM ADC and realizes the infrared readout circuit of 2k×2k array. By improving the integral-reset module and adding a low-power pre-comparator, the overall power consumption of the pixel unit is only 0.65 μW under the typical light intensity value of 20 nA. Meanwhile, the comparator module is no longer limited by power consumption, and the input-output nonlinear error is only 0.105%. The charge processing capacity reaches 3.1e^- and the center spacing of a single pixel is 20 μm, which provides a scheme for realizing low power consumption and high sensitivity infrared focal plane digital readout circuit.