Researching | A 28 nm 576K RRAM-based computing-in-memory macro featuring hybrid programming with area efficiency of 2.82 TOPS/mm2

Journal of Semiconductors, Volume. 46, Issue 6, 062304(2025)

A 28 nm 576K RRAM-based computing-in-memory macro featuring hybrid programming with area efficiency of 2.82 TOPS/mm²

Siqi Liu¹, Songtao Wei¹, Peng Yao^1、*, Dong Wu¹, Lu Jie¹, Sining Pan¹, Jianshi Tang¹, Bin Gao^1,2, He Qian¹, and Huaqiang Wu^1,2

Author Affiliations

¹School of Integrated Circuits, Tsinghua University, Beijing 100083, China

²International Innovation Center of Tsinghua University, Shanghai 200062, China

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References(17)

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[3] K Lee, J Kim, J Park. A 28-nm 50.1-tops/w p-8t sram compute-in-memory macro design with bl charge-sharing-based in-sram dac/adc Operations. IEEE J Solid State Circuits, 59, 1926(2024).

[4] J H Song, X Y Tang, H Y Luo et al. A 4-bit calibration-free computing-In-memory macro with 3T1C current-programed dynamic-cascode multi-level-cell eDRAM. IEEE J Solid State Circuits, 59, 842(2024).

[5] W Wan, R Kubendran, C Schaefer et al. A compute-in-memory chip based on resistive random-access memory. Nature, 608, 504(2022).

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[7] P Chi, S C Li, C Xu et al. PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 27(2016).

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[9] M Le Gallo, R Khaddam-Aljameh, M Stanisavljevic et al. A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nat Electron, 6, 680(2023).

[10] W H Huang, T H Wen, J M Hung et al. A nonvolatile Al-edge processor with 4MB SLC-MLC hybrid-mode ReRAM compute-in-memory macro and 51.4-251TOPS/W. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 15(2023).

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[13] S D Spetalnick, M Y Chang, S Konno et al. A 2.38 MCells/mm2 9.81−350 TOPS/W RRAM compute-in-memory macro in 40nm CMOS with hybrid offset/IOFF cancellation and ICELLRBLSL drop mitigation. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 1(2023).

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Siqi Liu, Songtao Wei, Peng Yao, Dong Wu, Lu Jie, Sining Pan, Jianshi Tang, Bin Gao, He Qian, Huaqiang Wu. A 28 nm 576K RRAM-based computing-in-memory macro featuring hybrid programming with area efficiency of 2.82 TOPS/mm²[J]. Journal of Semiconductors, 2025, 46(6): 062304

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Paper Information

Category: Research Articles

Received: Oct. 12, 2024

Accepted: --

Published Online: Jun. 30, 2025

The Author Email: Peng Yao (PYao)

DOI:10.1088/1674-4926/24100017

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