Fig. 1. (Color online) 576k macro architecture and configuration.

Fig. 2. (Color online) (a) Proposed 576k 2T2R array and WL segmentation diagram; finer control across column direction in (b) verify mode and (c) calculation mode.

Fig. 3. (Color online) (a) Structure of DSDC-ADC. (b) Timing diagram of the proposed DSDC-ADC and comparison.

Fig. 4. (Color online) (a) Drawbacks of 1T1R and 2T2R programming modes. (b) Working flow of hybrid programming mode.

Fig. 5. (Color online) (a) Pulse number required for all tested devices under different modes. (b) Failure rate under different programming modes.

Fig. 6. (Color online) Distribution of 2T2R conductance with 6 μS tolerance setting utilizing (a) 1T1R, (b) 2T2R, and (c) hybrid programming mode.

Fig. 7. (Color online) (a) Conductance values of positive 1T1R after programming. (b) Conduactance values of negative1T1R after programming.

Fig. 8. (Color online) (a) RRAM relaxation under 3 programming modes. (b) Distribution of voltages across RRAM cells of the final step of SET programming.

Fig. 9. (Color online) (a) Die photo and core layout. (b) Power and area breakdown.

Fig. 10. (Color online) (a) Multi-bit programming results using hybrid programming mode; (b) comparison of three programming modes.

Fig. 11. (Color online) (a) MVM test results with 32 input parallelism. (b) MVM test results with 128 input parallelism.