Fig. 1. Wafer-bonding technology. (a) Process flow of O₂ plasma assisted direct bonding of InP on SOI^[37]; (b) process flow of die-to-die/wafer adhesive bonding via DVS-BCB^[39]

Fig. 2. Wafer-bonding integrated Ⅲ‒Ⅴ lasers on Si. (a) Cross-sectional schematic of wafer-bonding structure^[40]; (b) wavelength-tunable Ⅲ‒Ⅴ micro-ring laser on silicon^[45]; (c) optical frequency comb laser on Si^[46]; (d) evanescent-wave coupled Ⅲ‒Ⅴ QD DFB laser on silicon^[48]

Fig. 3. Heterogeneous integration of laser by micro-transfer printing^[57]. (a) Schematic of heterogeneous integration of Ⅲ‒Ⅴ optoelectronic devices on a silicon photonics wafer by micro-transfer printing in a parallel manner; (b) process flow of micro-transfer printing for Ⅲ‒Ⅴ optoelectronic devices

Fig. 4. Defect-suppression techniques of Ⅲ‒Ⅴ directly grown on Si. (a) APB elimination^[69-71,73]; (b) TDs reduction^[76-79]; (c) thermal stress relaxation^[83-85]

Fig. 5. Ⅲ‒Ⅴ selective heteroepitaxy on Si. (a) 920 nm InP DFB lasers directly grown on Si substrates by selective heteroepitaxy technique via ART^[92]; (b) GaAs nano-ridge lasers on Si by selective heteroepitaxy technique^[93]

Fig. 6. Ⅲ‒Ⅴ lasers direct epitaxial grown on Si. (a) Schematic of InAs/GaAs QD laser on 4° offcut Si (001) substrate^[69]; (b) wavelength tunable InAs QD laser on Si^[100]; (c) schematic diagram of 20 GHz InAs QD mode-locked laser directly grown Si and optical frequency combs^[102]; (d) Si-based multi-wavelength laser via external cavity self-injection locking technique^[103]

Fig. 7. Ⅲ‒Ⅴ lasers directly grown on SOI. (a) Ⅲ‒Ⅴ nanolaser on SOI via selective heteroepitaxy^[105]; (b) Ⅲ‒Ⅴ FP ridge lasers on SOI^[109]

Fig. 8. Ⅲ‒Ⅴ lasers grown in SOI recess for coupling with waveguides. (a) Ⅲ‒Ⅴ laser grown in SOI recess^[117]; (b) embedded lasers in SOI recess, coupled to silicon waveguides^[118]; (c) 2.3 µm GaSb-based lasers grown in SOI recess coupled with SiN waveguide^[119]

Fig. 9. Ⅲ‒Ⅴ laser integration on Si via selective lateral heteroepitaxy. (a) Schematic of selective lateral heteroepitaxy of Ⅲ‒Ⅴ on SOI^[88]; (b) 3D schematic of Ⅲ‒Ⅴ on-chip lasers coupled to Si waveguide via selective lateral heteroepitaxy technique^[124]