Silicon-based optoelectronic integration (silicon photonics, SiPh) aims to leverage the advantages of optical interconnects, such as high bandwidth, low latency, and low power consumption, to achieve electronic computing with optical data transmission both on-chip and between chips. It serves as an enabling technology for future applications such as chip interconnects, high-performance computing, and AI computing centers. However, the lack of silicon-based on-chip lasers remains the primary obstacle to the development of SiPh. Silicon is an indirect bandgap semiconductor, leading to the inability to emit light efficiently. In contrast, Ⅲ?Ⅴ compound materials (such as GaAs, InP, InAs, and GaSb) are direct bandgap semiconductors, which can be used for the fabrication of high-performance laser sources on Si. Therefore, integrating Ⅲ?Ⅴ materials on Si to realize silicon-based Ⅲ?Ⅴ lasers is an essential step for the development of SiPh.

For the integration of Ⅲ?Ⅴ lasers on Si, three predominant approaches have been developed over the last decades, namely hybrid integration, heterogeneous integration, and monolithic integration. Hybrid integration couples the pre-fabricated Ⅲ?Ⅴ laser with the silicon photonic passive chip through packaging technology, for the realization of a single SiPh chip. Although this scheme can utilize the existing commercial laser platform for laser fabrication to ensure high performance, the packaging process requires extremely high alignment accuracy, leading to high cost and incompatibility with large-scale integration applications. Heterogeneous integration, such as wafer-bonding technology, can effectively avoid the lattice and polarity mismatch problems between the silicon substrate and Ⅲ?Ⅴ materials, and is relatively mature. This technology has been used in optical module products by companies like Intel. However, the wafer-bonding method still faces challenges such as thermal management at the multi-material interface, high process complexity, and low manufacturing throughput. The micro-transfer printing approach, which is different from wafer-bonding, involves taking the pre-fabricated Ⅲ?Ⅴ laser chips using a polydimethylsiloxane (PDMS) stamp through “pick-up and placement” operations, aligning them with high precision onto the already defined silicon photonic chips, and performing high-temperature annealing to enhance the adhesion between the laser chip and the silicon photonic chip. This technology can define the PDMS stamp as an array, allowing multiple laser chips to be picked up and simultaneously placed on the silicon photonic chip in each micro-imprinting process to meet the requirements of large-scale production. However, this technology also requires high alignment accuracy of the transfer equipment, which will increase the cost. Monolithic integration, by directly growing Ⅲ?Ⅴ materials on Si, is regarded as the truly wafer-scale and low-cost production method for the realization of on-chip light sources for SiPh. Due to the differences in lattice constant, polarity, and thermal expansion coefficient between Ⅲ?Ⅴ materials and Si, epitaxial growth of Ⅲ?Ⅴ materials on Si faces crystal quality issues, including mismatch defects, anti-phase domains (APDs), and thermal cracks. Many approaches have been demonstrated to solve these problems in order to obtain high-quality Ⅲ?Ⅴ epi-layers on Si platforms, which include the use of offcut Si (001) substrates, intermediate buffer layers, annealing processes, and patterned silicon substrates. Strained Ⅲ?Ⅴ dislocation filter layers (such as InGaAs/GaAs) are also grown to decrease the defect density of Ⅲ?Ⅴ materials on Si. To avoid the thermal crack problem, researchers have tried patterned substrates with underlying voids and increased the cooling time after growth to relieve thermal stress. Benefiting from these methods, high-quality Ⅲ?Ⅴ materials with defect density as low as 10⁶ cm^-2 and smooth surfaces have been achieved on Si. Based on the material growth, high-performance Ⅲ?Ⅴ lasers with low threshold current, high output power, and long lifetime are grown and fabricated on Si substrates. The selective heteroepitaxy growth method has also been developed to integrate Ⅲ?Ⅴ lasers butt-coupled with silicon passive components (such as silicon waveguides) on the same SiPh platform, which can solve the alignment problem. Moreover, Ⅲ?Ⅴ nano-lasers based on selective lateral epitaxial growth technology have attracted extensive attention recently due to their unique advantages, such as high flexibility and compatibility with SiPh fabrication. Although this method can grow defect-free Ⅲ?Ⅴ on Si by means of defect-trapping structures, the micro-sized Ⅲ?Ⅴ materials cannot support high output power lasing performance and are difficult to realize for electrically pumped applications. However, this method demonstrates strong technical potential and application prospects in the fabrication of Ⅲ?Ⅴ photodetector arrays.

As the core component of SiPh chips, Ⅲ?Ⅴ laser sources on silicon substrates have always been a research hotspot and key technical challenge in both the academic and industrial fields. Many approaches have been developed to realize Ⅲ?Ⅴ lasers on Si platforms, such as heterogeneous integration (including wafer-bonding and micro-transfer printing) and monolithic integration. Although the wafer-bonding approach has been commercialized in small-volume production, its productivity and yield should be further improved to meet the needs of large-scale integration applications. Monolithic integration by direct epitaxy is regarded as the true wafer-scale integration method, but the technological level, including improvements in crystal quality and coupling approaches, still requires substantial research and development.