Microelectronics, Volume. 54, Issue 1, 110(2024)

An U-Shaped High-K Dielectric Film Trench Gate Vertical Field Plate LDMOS

QIAN Tu, DAI Hongli, ZHOU Chunxing, and CHEN Weiyu
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    References(12)

    [2] [2] ZHANG B, ZHANG W, ZHU L, et al. Review of technologies for high-voltage integrated circuits [J]. Tsinghua Science and Technology, 2022, 27(3): 495-511.

    [3] [3] TANG P P, WANG Y, BAO M T, et al. Improving breakdown performance for SOI LDMOS with sidewall field plate [J]. Micro & Nano Letters, 2019, 14(4): 420-423.

    [5] [5] YAO J F, GUO Y F, ZHANG Z Y, et al. Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars [J]. Chinese Physics B, 2020, 29(3): 538-545.

    [6] [6] CHEN W Z, HUANG Y X, HUANG Y, et al. A super-junction SOI-LDMOS with low resistance electron channel [J]. Chinese Physics B, 2021, 30(5): 608-613.

    [7] [7] ZHANG C, LI Y, YUE W, et al. A novel LDMOS with quadruple RESURF effect breaking silicon limit [C] // 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). Xi’an, China. 2019: 1-3.

    [10] [10] WU L, SU S, CHEN X, et al. A deep trench super-junction LDMOS with double charge compensation layer [J]. Journal of Semiconductors, 2022, 43(10): 107-112.

    [12] [12] LEI J, HU S, YANG D, et al. Performance analysis of a novel trench SOI LDMOS with centrosymmetric double vertical field plates [J]. Results in Physics, 2019, 12: 810-815.

    [14] [14] JING D, HUANG M, CHENG J, et al. A new low specific on-resistance Hk-LDMOS with N-poly diode [J]. Superlattices and Microstructures, 2017, 101: 180-190.

    [15] [15] WU L, HU L, ZHU L, et al. Ultralow specific on-resistance high-k LDMOS with vertical field plate [J]. Journal of Semiconductors, 2018, 39(10): 57-61.

    [16] [16] CAO Z, DUAN B X, SONG H T, et al. Novel superjunction LDMOS with a high-K dielectric trench by TCAD simulation study [J]. IEEE Transactions on Electron Devices, 2019, 66(5): 2327-2332.

    [17] [17] ZHANG W, ZHANG B, QIAO M, et al. A novel vertical field plate lateral device with ultralow specific on-resistance [J]. IEEE Transactions on Electron Devices, 2013, 61(2): 518-524.

    [18] [18] CHENG J, CHEN W, LIN J, et al. Potential of utilizing high-k film to improve the cost performance of trench LDMOS [J]. IEEE Transactions on Electron Devices, 2019, 66(7): 3049-3054.

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    QIAN Tu, DAI Hongli, ZHOU Chunxing, CHEN Weiyu. An U-Shaped High-K Dielectric Film Trench Gate Vertical Field Plate LDMOS[J]. Microelectronics, 2024, 54(1): 110

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    Paper Information

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    Received: Aug. 4, 2023

    Accepted: --

    Published Online: Aug. 7, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230302

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