Fig. 1. Schematic diagram for layered processing of alignment mark

Fig. 2. Front view of AH53 mark

Fig. 3. 5th order diffraction efficiency at different harmonic numbers

Fig. 4. Curves of wafer quality and signal-to-noise ratio changing with groove depth. (a) Wafer quality;(b) signal-to-noise ratio

Fig. 5. Curves of wafer quality and signal-to-noise ratio changing with groove width. (a) Wafer quality;(b) signal-to-noise ratio

Fig. 6. Curves of wafer quality and signal-to-noise ratio changing with resist. (a) Wafer quality; (b) signal-to-noise ratio

Fig. 7. Curves of wafer quality and signal-to-noise ratio changing with oxide layer. (a) Wafer quality; (b) signal-to-noise ratio

Fig. 8. Schematic diagrams of sidewall deformation. (a) Sidewall angle;(b) sidewall of arc

Fig. 9. The influence of the number of layers on the calculation accuracy under different sidewall angles. (a) 120°; (b) 110°; (c) 100°

Fig. 10. The influence of number of harmonic on calculation accuracy under different sidewall angles

Fig. 11. Curves of wafer quality and signal-to-noise ratio changing with sidewall angle. (a) Wafer quality; (b) signal-to-noise ratio

Fig. 12. Schematic diagrams of sidewall of arc. (a) Sidewall of concave arc; (b) sidewall of convex arc

Fig. 13. Curves of wafer quality and signal-to-noise ratio changing with sidewall of concave arc. (a) Wafer quality; (b) signal-to-noise ratio

Fig. 14. Curves of wafer quality and signal-to-noise ratio changing with sidewall of convex arc. (a) Wafer quality; (b) signal-to-noise ratio

Fig. 15. Schematic diagram of asymmetric mark

Fig. 16. Comparison of simulation results of two methods

Fig. 17. Marked wafer quality measurement

Fig. 18. Cross section of mark

Fig. 19. Comparison between simulation results and experimental results