Fig. 1. Key fabrication process of the silicon APD array and microscope photograph of partial fabricated arrays. (a) Epitaxial wafer growth; (b) implantation of P-stopper; (c) implantation of guard-ring and rapid thermal annealing; (d) implantation for ohm contact and rapid thermal annealing; (e) antireflection film deposited and etched; (f) TiAu deposition and patterning; (g) CMP on the back side; (h) metallization on the back side; (i) microscope photograph of partial fabricated arrays.

Fig. 2. Brief schematic of the APD arrays measurement system (a monochromatic light source was used in the actual measurement).

Fig. 3. Uniformity of 2 × 64 fabricated APD arrays. (a) Dark currents of all pixels as a function of reverse bias voltage; (b) profile of breakdown voltage and dark current at unity gain; (c) two-dimensional mapping of dark current at unity gain (unit, pA); (d) two-dimensional mapping of V_br for pixels.

Fig. 4. Measurement results of response and multiplication characteristics for one pixel in the fabricated APD arrays. (a) Response characteristics at unity gain; (b) reverse I-V curves near breakdown state.

Fig. 5. Dynamic characteristics for one pixel. (a) Capacitance versus reverse voltage; (b) quick optical pulse response of standard ET2020 APD; (c) quick optical pulse response of fabricated APD in this work.