Journal of Semiconductors, Volume. 46, Issue 3, 032201(2025)
A 0.0012-mm2 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of fcarrier/2
Fig. 1. (Color online) Simplified block diagram of the WPDT system.
Fig. 2. (Color online) Block diagram of the proposed BPSK demodulator.
Fig. 3. (Color online) Schematics of (a) prior XOR-PLL, and (b) proposed LPF-Less PLL.
Fig. 5. (Color online) Simulated timing of the LPF-Less PLL with input phase transition.
Fig. 7. (Color online) Operation process: (a) DRMAX = 0, (b) DRMAX = 1.
Fig. 8. (Color online) Simulation at the data rate of (fcarrier/8) with high-Q coils: (a) DRMAX = 1, (b) DRMAX = 0.
Fig. 9. (Color online) Chip photograph with the core layout of the BPSK demodulator.
Fig. 10. (Color online) Measurement results at the maximum data rate 6.78 Mb/s.
Fig. 11. (Color online) Measurement with high-Q coils: (a) setup, (b) results at 1.695 Mb/s.
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Xinyu Shen, Zhao Zhang, Jie Yang, Jian Liu, Nanjian Wu, Mohamad Sawan, Liyuan Liu. A 0.0012-mm2 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of fcarrier/2[J]. Journal of Semiconductors, 2025, 46(3): 032201
Category: Research Articles
Received: Oct. 14, 2024
Accepted: --
Published Online: Apr. 27, 2025
The Author Email: Zhao Zhang (ZZhang)