[3] [3] ZHANG X F, WEI Y. Chip-package interaction and reliability improvement by structure optimization for ultralow- interconnects in flip-chip packages ［J］. IEEE Trans Dev & Mater Reliab, 2012, 12(2): 462-469.

[4] [4] UCHIBORI C J, ZHANG X F, HO P S, et al. Effects of chip-package interaction on mechanical reliability of Cu interconnects for 65 nm technology node and beyond ［C］ // Proceed IEEE Int Interconn Technol Conf. Burlingame, CA, USA. 2006: 196-198.

[5] [5] RAGHAVAN S, SCHMADLAK I, SITARAMAN S K. Interlayer dielectric cracking in back end of line (BEOL) stack ［C］ // Elec Compon & Technol Conf. San Diego, CA, USA. 2012: 1467-1474.

[6] [6] UCHIBORI C, ZHANG H, PAUL S, et al. Investigation of interconnect design on chip package interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip chip package ［C］ // Int Interconn Technol Conf. Burlingame, CA, USA. 2008: 150-152.

[7] [7] UCHIBORI C J, LEE M, ZHANG X F, et al. Chip package interaction analysis for Cu/ultra low-k large die flip chip ball grid array ［C］ // IEEE 9th VLSI Packag Workshop. Kyoto, Japan. 2008: 87-90.

[8] [8] MERCADO L L, GOLDBERG C, KUO S M, et al. Analysis of flip-chip packaging challenges on copper/low-k interconnects ［J］. IEEE Trans Dev & Mater Reliab, 2003, 3(4): 111-118.

[10] [10] LIN L, WANG J, WANG L, et al. The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process ［J］. Microelec Reliab, 2016, 65(10): 198-204.

[11] [11] LEE M W, KIM J Y, KIM J D, et al. Below 45 nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping ［C］ // Proceed 60th ECTC. Las Vegas, NV, USA. 2010: 1623-1630.

[12] [12] LIN L, WANG J, YANG C. Stress modeling for the impacts of flip chip process on the ultralow-k chips ［C］ // 15th ICEPT. Chengdu, China. 2014: 740-744.

[14] [14] WANG L, XU C, LIN L,et al. Thermal stress analysis of the low-k layer in a flip-chip package ［J］. Microelec Engineer, 2016, 163(9): 78-82.

[15] [15] MERCADO L, GOLDBERG C, KUO S M. A simulation method for predicting packaging mechanical reliability with low k dielectrics ［C］ // Proceed IEEE Int Interconn Technol Conf. Burlingame, CA, USA. 2002: 119-121.

[16] [16] YANG C, WANG L, YU K H, et al. Assess low-k/ultralow-k materials integrity by shear test on bumps of a chip ［J］. J Mater Sci: Mater Elec, 2018, 29(19): 16416-16425.

[17] [17] ZHANG X F, RYU S K, HUANG R, et al. Impact of process induced stresses and chip-packaging interaction on reliability of air-gap interconnects ［C］ // Proceed IEEE Int Intercon Technol Conf. Burlingame, CA, USA. 2008: 135-137.