Fig. 1. PPD cross-section diagram and potential diagram along cutline B-B'. (a) Simple cross-section of PPD; (b) potential diagram along cutline B-B'

Fig. 2. 2D TCAD electrostatic potential simulation and simplified cross section of the PPD along A₁‒A₄. (a) V_TG=0.2 V; (b) V_TG=0.4 V

Fig. 3. Model simulation flow of the integration and charge overflow

Fig. 4. 2D TCAD electrostatic potential simulation

Fig. 5. Potential of TCAD simulation and model calculation results under different TG voltages. (a) V_TG = 0.5 V; (b) V_TG = 0.6 V; (c) V_TG = 0.7 V

Fig. 6. Comparison between the proposed model results and TCAD simulations for different light intensities. (a) Variation of the PPD potential for different TG voltages; (b) variation of FWC for different TG voltages

Fig. 7. Simulation results of charge accumulation and charge overflow with time under the condition of light luminance intensity of 90 lx and V_TG of 0.7 V. (a)(b) Curves of charge accumulation and charge overflow with time at light luminance intensity of 90 lx; (c)(d) curves of charge accumulation and charge overflow with time when V_TG is 0.7 V

Fig. 8. Test chip. (a) Photograph of the test chip; (b) LOFIC pixel structure of the test chip; (c) timing diagram of the pixel

Fig. 9. Variation of charge accumulation with light luminance intensity under different TG voltages. (a) Model results; (b) test results

Fig. 10. Test results of total amount of overflow electrons under fixed grid voltage and different light luminance intensities. (a) V_TG = 0.4 V; (b) V_TG = 0.6 V