In 1964, Hughes first mentioned the effect of high-energy γ-rays on the MOSFET structure, and then in 1988, this type of PMOS detector was named as RADFET^[1]. Compared with gas detectors, scintillation detectors, semiconductor diodes, and other radiation detectors, RADFET radiation dosimeters have the advantages of easy integration, small size, light weight, and very low power consumption^[2−6]. They are widely used in fields such as aerospace exploration, nuclear industry protection, and personal dose monitoring for medical radiation^[7−11]. Methods to improve the sensitivity of RADFET mainly include increasing the thickness of the gate oxide layer and adopting stacked structures^[12−16]. Liu from peking university prepared a RADFET with a gate oxide thickness of 420 nm in the laboratory, achieving a maximum sensitivity of 229 mV/Gy^[17].

However, up till now, no domestically-produced RADFET products were fabricated in an 8-inch process. Therefore, based on CUMEC 8-inch 90 nm pilot line, the RADFET research is carried out to achieve domestic chip production.

As shown in Fig. 1, the structure of RADFET is a typical PMOS transistor with four ports, drain, gate, source, and substrate. When the voltage applied to the gate does not reach the threshold voltage, there is no conduction path between the source and the drain regions, with the device being turned off. When the gate voltage exceeds the threshold voltage, a hole inversion layer forms beneath the gate oxide, which allows conduction between the source and the drain regions, thus turning the device on.

The general formula for the threshold voltage of the PMOS transistor is

1Vt=Φms−Q0COX−QA(−2ΦFn)COX−2ΦFn,

where Φ_ms is the work function difference between the gate and the silicon substrate, and C_OX is the capacitance per unit area of the gate oxide, and Φ_Fn is the substrate Fermi potential, and Q_A(−2Φ_Fn) is the charge density of ionized donors in the depletion region at strong inversion, and Q₀ is the effective interface charge density, determined by the oxide charge, closely related to radiation-induced charge and radiation-induced interface states, and is the primary cause of radiation-induced threshold voltage shift. The oxide charge distribution in the MOS structure is illustrated in Fig. 2, and these charges can be broadly categorized into four types: firstly, interface trap charges at the silicon-gate oxide interface, secondly, fixed charges within 20 nm near the silicon-gate oxide interface, thirdly, oxide trap charges widely present in the oxide layer, fourthly, mobile ionic charges in the oxide layer, typically sodium and potassium ions.

When a PMOS device is exposed to γ-rays, the radiation energy creates electron−hole pairs in the gate oxide layer. When a positive voltage is applied to the gate, due to the much higher mobility of electrons than that of holes in the oxide layer, electrons are quickly removed by the electric field, while holes move slowly within the oxide layer. These holes are trapped by interface traps and traps within the oxide layer, becoming interface trap charges and oxide trap charges, respectively. This results in an increase in the effective interface charge density Q₀ of the PMOS, which in turn increases the threshold voltage. Because Q₀ is proportional to the total dose and the threshold voltage variation (∆V_t) is proportional to Q₀, ∆V_t is proportional to the total dose. As a consequence, the intensity of radiation can be estimated by measuring the shift in threshold voltage of the RADFET before and after irradiation.

According to the datasheet from a foreign company, the RADFET utilizing a gate oxide thickness of 400 nm is used to detect a total dose of 1 rad to 100 krad with the maximum sensitivity of 55 mV/100rad, which has been widely used in various detection field. Therefore, a gate oxide thickness of 400 nm and a W/L ratio of 300 µm/50 µm are chosen to design domestic RADFET chips for detecting a total dose of 1 rad to100 krad. The main process flow of RADFET fabrication is shown in Fig. 3, which consists of the following steps.

(a) Both N-type and P-type doping are used sequentially to form the body region and the source/drain regions of the PMOS. After each implantation step, thermal oxidation is performed to increase the junction depth.

(b) Since thick gate oxide layers grow slowly through only dry thermal oxidation and cannot continue to grow later on, and even due to insufficient density, dry thermal oxidation methods cannot be used. Moreover, the quality of SiO₂ oxide layers grown by wet oxidation cannot be guaranteed. Therefore, a combination of dry-wet-dry oxidation methods is adopted.

(c) Threshold voltage adjustment implantation with boron ions is conducted after the formation of the PMOS gate oxide layer. On one hand, defects and traps in the gate oxide layer will significantly increase, enhancing the ability to capture holes and thus improving device sensitivity. On the other hand, it allows for precise control of the device threshold voltage.

(d) Finally, the gate electrode formation with an aluminum gate process instead of a polysilicon gate process is considered for the following two main reasons. Firstly, the conductivity of polysilicon gates is not as good as that of aluminum gates. Secondly, the resistance of polysilicon gate can be reduced by increasing its thickness, but the doping concentration at bottom of polysilicon is relatively low without high thermal diffusion, which increases threshold voltage as a result of the polysilicon bottom depletion.

Based on the above process flow, the PMOS was simulated using Sentaurus process simulation tools, resulting in the device structure shown in Fig. 4. The junction depth of both the drain and source exceeds 3 µm, representing a deep diffusion junction that enhances the device source−drain breakdown voltage and stabilizes performance. Simulation results exhibit a drain-to-source breakdown voltage (BV_DS) of over −50 V, a threshold voltage of approximately −2.2 V, and a leakage current of 8 µA, with all simulation values being comparable to similar existing products.

The layout of the RADFET chip with a 610 µm × 610 µm size, includes two identical PMOS devices with a W/L ratio of 300 µm/50 µm, as illustrated in Fig. 5. Additionally, a parasitic diode is integrated. The PAD size of the chip is 100 µm × 100 µm. It should be noted that the gate oxide of the PMOS with a 400 nm thick can sustain a high breakdown voltage, so no additional ESD device is designed to protect the gate from ESD damage.

The RADFET chip measurement is divided into pre-irradiation and post-irradiation tests. The former uses WAT (Wafer Acceptance Test) to monitor parameters, such as the PMOS threshold voltage and BV_DS. The latter involves irradiation test for the RADFET dies packed in a DIP-14 package, which monitors the shift in threshold voltage before and after irradiation.

The transfer and the output characteristics of the PMOS are shown in Fig. 6. It can be seen that when the current is −10 µA, the threshold voltage is approximately −2 V, consistent with the previous simulation design value. Additionally, the output characteristic curve of the PMOS exhibits good saturation characteristics, with a saturation voltage exceeding −60 V and the saturation current increasing with gate to source voltage (V_GS).

A map test was conducted to check the uniformity of RADFET across the entire 8-inch wafer, as illustrated in Fig. 7. The number of test die is over 90. The variation in PMOS breakdown voltage (BV_DS) and leakage current (ioff) are less than 2% and 3%, respectively, exhibiting very uniform distribution. However, the threshold voltage (Vtlin_cal) difference in several dies on the right and the bottom sides of the wafer reach about −10% variation. This is possibly due to lithography issues, which can be optimized by process.

The irradiation experiment is conducted using a cobalt source with a dose rate of 50 rad(Si)/s. Current RC_I is forced into the RADFET, connected in RC configuration, as shown in Fig. 8. The gate and drain are shorted to the ground, and source is connected to the constant current source. The voltage at the source (RC_V) is measured, and this voltage is called "RC threshold voltage". The subthreshold current of RADFET is about 1 µA, as illustrated in Fig. 6(b). Therefore, in principle, any read-out current (RC_I) value above 5 µA can be chosen. However, for best temperature compensation, the RC_I value of 10 µA is utilized. Fig. 9 depicts the variation curve of threshold voltage shift with total dose. Fig. 10 compares the characteristics curve before and after irradiation at 100 krad (Si), which indicates a significant negative shift in threshold voltage after post-irradiation, and this is because that the threshold voltage is increased after irradiation. At a total dose of 100 krad(Si), the increase in threshold voltage is approximately 1.37 V. However, compared to existing products, the sensitivity of the RADFET in this work is still relatively lower. The improvements include the following directions. Firstly, pure aluminum process rather than an alloy of aluminum and copper will be adopted to eliminate the effects of copper atoms. Secondly, a thicker gate oxide will be utilized, such as 500 nm, to increase sensitivity.

In summary, this paper established the RADFET fabrication process flow, and completed process simulation and device electrical parameter simulation. The simulated results keep competitive with those of the existing products. Based on the process flow and device structural parameters, the RADFET chip layout design was completed. Wafer measurement results show that the pre-irradiation electrical parameters are consistent with TCAD simulation values, and map test results indicate good uniformity across the wafer. Post-irradiation measurement results demonstrate good consistency of RADFETs, achieving a fantastic radiation detection function.