The gate electrode of thin film transistor(TFT) is a step in cross section, it is covered by gate insulator(GI), source and data electrode(SD electrode) in sequence, and the degree of coverage is measured by the step coverage, which is the ratio of the horizontal thickness to the vertical thickness of GI layer at the step. In this paper, combining the manufacturing process of HADS product in Chongqing BOE company, the influence of gate thickness and profile on the GI layer step coverage is studied. Then, the difference of SD etching degree between step and non-step is explored based on step coverage. After that, the relationship between gate profile, step coverage, Cu corrosion and other defects are analyzed based on defect information in mass production. At last, the corresponding yield up measures are proposed. The experimental results show that the tate profile is a key factor affecting step coverage, and gate profile has a negative linear relationship with GI coverage. When the gate thickness varies from 280 nm to 500 nm, the GI coverage decreases by 20% for every 10° increase in the gate profile. SD layer covers the step, and will be thinned at this place, which leads to an increase in the degree of SD etching. If the gate profile is large, the GI layer at the step will be thinned or generates micro-cracks, the corrosive medium in manufacturing process will pass through the thinned GI layer or crack to react with gate electrode to form corrosion. Whats more, a larger gate profile will cause SD line to be open at the step. A gentle gate profile can be obtained to avoid the above yield risk by changing etchant, adjusting etchant composition, optimizing etch process. In addition, it is a useful method to adjust GI deposition parameter to improve GI coverage to avoid gate corrosion; and the solution containing improving photo-resist adhesion, widening the SD line at the step can be tried to avoid SD line open.