Fig. 1. Electric pulse leading edge interference equivalent circuit

Fig. 2. Coupling interference transmission path

Fig. 3. Topology of series inductive energy pulse forming line (SIE_PFL)

Fig. 4. SIE_PFL control logic and output pulse

Fig. 5. Principle circuit of IE_PFL heavy load adaptive function

Fig. 6. Simulation results and picture of ULI_PoP

Fig. 7. Comparison of ultra-fast gate driver and common gate driver

Fig. 8. Pulse width modulation

Fig. 9. Waveform of modulated 5 ns rectangular wave

Fig. 10. Heavy load adaptive output pulse

Fig. 11. Multi-stage stacking experiment results

Fig. 12. 200 kHz repetition rate pulse