Optical Communication Technology, Volume. 49, Issue 4, 46(2025)

Design of high-speed dual-channel parallel 16b/18b encoder for HDMI2.1 protocol

LI Xiaopeng1,2, XIONG Taiping1,2, CUI Gengshen2, WU Mingjun1,2, and ZENG Bicheng1,2
Author Affiliations
  • 1Guangxi Key Laboratory of Image and Graphic Intelligent Processing, Guilin University of Electronic Technology, Guilin Guangxi 541004, China
  • 2Nanning Research Institute, Guilin University of Electronic Technology, Nanning 530000, China
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    References(11)

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    [2] [2] ZENG J,YANG J,ZHANG L,et al. FPGA implementation of fixed-latency command distribution based on aurora 64B/66B [J]. IEEE Transactions on Nuclear Science,2024,71(6):1348-1356.

    [3] [3] POPA S,COLIBAN R M,IVANOVICI M. An optimal implementation of an 8b/10b encoder for Xilinx FPGAs [C]//IEEE. Proceedings of 2022 International Symposium on Electronics and Telecommunications(ISETC). Timisoara:IEEE,2022:1-4.

    [5] [5] SONG C,JUNG H,CHANG K,et al. A 24-Gb/s MIPI C-/D-PHY receiver bridge chip with phase error calibration supporting FPGA-based frame grabber [J]. IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2024,32(4):714-727.

    [11] [11] CHEN Z J,ZHONG G H,BI Z. A high speed 8B/10B encoder/decoder design based on low cost FPGA [J]. Advanced Materials Research,2012,462:361-367.

    [12] [12] NANNIPIERI P,DAVALLE D,FANUCCI L. A novel parallel 8B/10B encoder:architecture and comparison with classical solution [J]. IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences,2018(7):1120-1122.

    [13] [13] SONG S,YIN H,ZHAO J,et al. An 8B/10B parallel encoder design for the polarity pre-processing [J]. Journal of Physics:Conference Series,2023,2450(1):012055-1-012055-7.

    [16] [16] WIDMER A X,FRANASZEK P A. A DC-balanced,partitioned-block,8B/10B transmission code [J]. IBM Journal of Research and Development,1983,27(5):440-451.

    [17] [17] POPA S,IVANOVICI M,COLIBAN R M. Optimal implementations of 8b/10b encoders and decoders for AMD FPGAs[J]. Electronics,2024,13(6):1062-1-1062-28.

    [18] [18] SUMA M S,REKHA S S. 16B/20B CODEC development and its ASIC implementation [C]//IEEE. Proceedings of 2009 International Conference on Future Computer and Communication. Kuala Lumpar:IEEE,2009:622-626.

    [23] [23] WIDMER A X. Partitioned DC balanced(0,6)16B/18B transmission code with error correction:6198413 B1[P]. 2001-03-06.

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    LI Xiaopeng, XIONG Taiping, CUI Gengshen, WU Mingjun, ZENG Bicheng. Design of high-speed dual-channel parallel 16b/18b encoder for HDMI2.1 protocol[J]. Optical Communication Technology, 2025, 49(4): 46

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    Paper Information

    Special Issue:

    Received: Nov. 17, 2024

    Accepted: Sep. 15, 2025

    Published Online: Sep. 15, 2025

    The Author Email:

    DOI:10.13921/j.cnki.issn1002-5561.2025.04.008

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