To meet the high-speed data transmission requirements of the high-definition multimedia interface（HDMI）2.1 protocol and address the latency issues caused by running disparity（RD）dependency in traditional 16b/18b encoders, a high-speed dual-channel parallel 16b/18b encoder design is proposed. By introducing a fast RD generation module and a dual-channel parallel r edundant architecture, the encoding process is optimized, enabling true parallel encoding. Experimental validation is conducted on the Xilinx Zynq UltraScale+MPSoC field-programmable gate array（FPGA）platform. The results demonstrate that at a 400 MHz clock frequency, the encoder achieves a data transmission rate of 14.4 Gb/s with low resource utilization（Block RAM usage of 62.5%）and a power consumption of only 2.636 W. This design significantly reduces encoding latency while maintaining stable linear delay characteristics.