The rapid advancement of data-intensive applications—such as high-performance computing, artificial intelligence, and ultrahigh‐speed optical communications—has exposed fundamental limitations in traditional electronic logic gates regarding processing speed, bandwidth, and energy efficiency. All-optical logic gates, which execute Boolean operations directly on light signals, provide ultrafast response, low power consumption, and seamless integration with silicon photonic platforms. Traditional design methodologies, however, depend extensively on manual parameter optimization of complex structures, leading to extended design cycles and substantial computational requirements. This research presents a systematic, automated inverse-design framework utilizing particle swarm optimization (PSO) to develop compact, robust silicon‐based optical logic gates—specifically OR, AND, and XOR—thereby reducing design complexity and accelerating device development.

We propose a PSO-driven inverse-design framework for diffraction-based optical logic gates on a silicon-on-insulator (SOI) platform. The device architecture comprises an input layer, two diffraction layers formed by 36 variable-length etched slots, and an output layer (Fig. 1). Each slot length, constrained between 0 μm and 2.3 μm with fixed 0.5 μm spacing, functions as a tunable phase-delay element. We encode logical 0 and 1 input states as phase shifts of 0° and 180°, respectively, at the two input ports, with a constant bias port phase of 180°. An enhanced PSO algorithm initializes a swarm of candidate structures (particles), each represented by a 36-dimensional vector of slot lengths. In each iteration, particles update their positions and velocities guided by individual and global best solutions, evaluated via 2.5D finite-difference time-domain (FDTD) simulations. The fitness function maximizes the minimum contrast ratio (CR)—defined by the power difference between the 1 and 0 outputs—over all four input combinations. Convergence occurs when the swarm’s global best CR stabilizes. Optimized designs for OR, AND, and XOR gates are derived by modifying the target output assignment during fitness evaluation. Optimized 2-layer geometries for the three gates are shown in Fig. 5. Fabrication on SOI (220 nm silicon thickness) utilizes electron-beam lithography and reactive-ion etching. Packaged chips, each integrating three gates, are mounted in fiber-array fixtures for optical characterization.

The PSO-designed logic gates demonstrate high contrast ratios and broad operational bandwidths. At the central telecommunication wavelength of 1550 nm, the minimum CRs for OR, AND, and XOR gates achieve 5.6 dB, 5.7 dB, and 6.3 dB, respectively (Tables 1-3). Light field distributions under all four input combinations verify correct logic functionality (Figs. 6, 8, 10). Over a 1530-1570 nm spectral range, each gate maintains CR >4.5 dB (OR & AND) or >3.5 dB (XOR), indicating robust wavelength tolerance (Figs. 7, 9, 11). Scanning electron microscope (SEM) images confirm accurate reproduction of the optimized slot geometries (Fig. 13). Insertion‐loss (IL) measurements—conducted with a tunable laser source and optical vector analyzer—reveal IL below 3 dB across all ports, with standard deviation under ±0.9 dB (Figs. 15‐17). These results align closely with 2.5D‐FDTD predictions, demonstrating both design accuracy and fabrication fidelity. Compared with recent implementations using empirical or topology-optimization methods, our inverse-design approach achieves a compact footprint (18 μm×9 μm) and competitive CRs without requiring nonlinear materials or active modulators (Tables 4‐6). Additionally, tolerance analysis—by uniformly offsetting all slot lengths by ±10 nm—yields CR variation under ±0.5 dB, demonstrating excellent robustness against fabrication imperfections.

We have developed and experimentally validated a PSO‐based inverse-design framework for compact, high-performance silicon photonic logic gates. Through optimization of 36 variable-length diffraction slots on an SOI platform, we achieve OR, AND, and XOR functionality with CRs exceeding 5.6 dB, low insertion loss, and broad C-band bandwidth (1530‐1570 nm). The proposed design workflow maintains full standardization, enabling rapid generation of specific logic functions by merely altering target output assignments. Future research directions include hybrid optimization strategies (e.g., PSO combined with deep learning), multi-layer diffraction networks for enhanced CR, and integration of on-chip phase modulators for dynamic reconfigurability. This research significantly advances the development of scalable all-optical computing devices in next-generation photonic integrated circuits.