Microelectronics, Volume. 55, Issue 1, 134(2025)

An Interconnect Delay Prediction Model for ASIC Chips Based on LightGBM

CHEN Lin, TAO Runzhe, XIE Yuchi, FU Qiutao, and DI Zhixiong
Author Affiliations
  • School of Information Science and Technology, Southwest Jiaotong University, Chengdu 611756, P R China
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    References(10)

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    [4] [4] HAN S S, KAHNG A B, NATH S, et al. A deep learning methodology to proliferate golden signoff timing[C]//Design, Automation & Test in Europe Conference & Exhibition. Dresden, Germany. 2014: 1-6.

    [5] [5] CHENG H H, JIANG I H, OU O. Fast and accurate wire timing estimation on tree and non-tree net structures[C]//2020 57th ACM/IEEE Design Automation Conference. San Francisco, CA, USA.2020: 1-6.

    [6] [6] BHASKER J, CHADHA R. Static timing analysis for nanometer designs: a practical approach[M]. New York: Springer, 2009: 101-120.

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    [8] [8] KE G L, MENG Q, FINLEY T, et al. LightGBM[C]//Proceedings of the 31st International Conference on Neural Information Processing Systems. Long Beach, CA, USA. 2017: 3149-3157.

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    CHEN Lin, TAO Runzhe, XIE Yuchi, FU Qiutao, DI Zhixiong. An Interconnect Delay Prediction Model for ASIC Chips Based on LightGBM[J]. Microelectronics, 2025, 55(1): 134

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    Paper Information

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    Received: Mar. 11, 2024

    Accepted: Jun. 19, 2025

    Published Online: Jun. 19, 2025

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.240056

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