Fig. 1. Readout integrated circuit. (a) System architecture; (b) operating timing in ITR mode

Fig. 2. Block diagram of single-column low-power pixel circuit structure

Fig. 3. Curve of g_m/I_d versus V_GS-V_th

Fig. 4. Cell pixel circuit layout

Fig. 5. Monte Carlo transient simulation of pixel circuit

Fig. 6. Voltage discrete case analysis. (a) V_int; (b) V_float

Fig. 7. Diagram of PGA working principle. (a) Sampling mode; (b) amplifying mode

Fig. 8. Single branch sampling circuit. (a) Schematic diagram; (b) timing diagram

Fig. 9. Double branch interleaved sampling circuit. (a) Schematic diagram; (b) timing diagram

Fig. 10. Column buffers time-sharing gating strategy. (a) Schematic diagram; (b) timing diagram

Fig. 11. Schematic diagram of operational amplifier structure and its small signal current. (a) FC; (b) ARFC

Fig. 12. Output buffer layout

Fig. 13. ARFC and FC operational amplifier AC characteristic. (a) Amplitude frequency curves; (b) phase frequency curves

Fig. 14. Large-signal step response of ARFC and FC operational amplifier

Fig. 15. Infrared focal plane readout integrated circuit layout

Fig. 16. Output response of signal chain under time-sharing gating strategy

Fig. 17. Overall noise simulation results

Fig. 18. Overall linearity of signal chain under different process corners

Fig. 19. Power consumption distribution of infrared focal plane readout integrated circuit