To solve the problem of high-power consumption of high-performance infrared array readout circuit, in this study, customized low power design is conducted. Interlacing sampling technology and time-sharing gating strategy of column-level buffer are adopted to overcome the characteristics of low time utilization and high idle power consumption. In the circuit design, the input pair of capacitive feedback trans-impedance amplifier in the pixel array is biased in the subthreshold region to exchange low current for high performance. Based on the single-ended output scenario of the output buffer, a new high current efficiency asymmetrical recycling folded cascode operational amplifier structure is proposed, which significantly reduces the power consumption and area. Compared with the traditional folded cascode structure, the power consumption is reduced by 62.5% under the similar performance index. Additionally, based on SMIC 0.13 μm 1P8M digital/analog hybrid integrated circuit technology, a 1280×1024 scale area array readout circuit is designed. The post simulation results show that the overall power consumption of the readout circuit is 190 mW at a high frame rate of 120 Hz, the parallel data transfer rate of eight channels is 2×10⁷ pixel/s, and the overall linearity exceeds 99.3%.