To meet the application requirements of large area array complementary metal-oxide semiconductor (CMOS) image sensors (CIS), a ramp signal generator with slope and sample mode adjustment is presented in this paper. The design, simulation, and layout are implemented using a 90 nm (1.2 V/2.8 V) 1P5M CIS process. This circuit design has a simple structure, small area, adjustable slope. The slope amplitude is greater than 0.5 V, reset time is less than 70 ns, differential nonlinearity is +0.018 LSB/−0.012 LSB, and integrated nonlinearity is +0.37 LSB/−0.013 LSB, which meets the design and engineering application requirements of large array CIS.