Microelectronics, Volume. 54, Issue 2, 235(2024)

Design of 56 Gbit/s Low-Power PAM4 SerDes Transmitter with Fractionally-Spaced FFE

WANG Xinwu1, ZHANG Changchun1,2, ZHANG Yi1, and WANG Jing1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    References(13)

    [1] [1] KIM J, BALANKUTTY A, ELSHAZLY A, et al. A 16-to-40 Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14 nm CMOS [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA,USA. 2015: 1-3.

    [3] [3] LIM B, KIM D, YOO C, et al. Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture[J]. Electronics Letters, 2020, 56(9): 431-432.

    [4] [4] CHANG Y, MANIAN A, KONG L, et al. An 80Gb/s 44-mW wireline PAM4 transmitter [J]. IEEE J Sol Sta Circ, 2018, 53(8): 2214-2226.

    [5] [5] SHIBASAKI T, DANJO T, OGATA Y, et al. A 56 Gb/s NRZ electrical 247 mW/lane serial-link transceiver in 28 nm CMOS [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA,USA. 2016: 64-65.

    [6] [6] STEFFAN G, DEPAOLI E, MONACO E, et al. A 64 Gb/s PAM-4 transmitter with 4-tap FFE and 2.26 pJ/b energy efficiency in 28 nm CMOS FDSOI [C] //IEEE International Solid-State Circuits Conference.San Francisco, CA, USA. 2017: 116-117.

    [7] [7] ZHENG X, DING H, ZHAO F, et al. A 50-112-Gb/s PAM-4 transmitter with a fractional-spaced FFE in 65-nm CMOS [J]. IEEE J Sol Sta Circ, 2020, 55(7):1864-1876.

    [8] [8] NAVID R, CHEN E H, HOSSAIN M, et al. A 40Gb/s serial link transceiver in 28 nm CMOS technology[J]. IEEE J Sol Sta Circ, 2014, 50(4): 814-82.

    [9] [9] PENG P, LAI S, WANG W, et al. A 100 Gb/s NRZ transmitter with 8-tap FFE using a 7 b DAC in 40 nm CMOS [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2020: 130-132.

    [10] [10] ZHENG X, ZHANG C, LV F, et al. A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS [C] // IEEE Custom Integrated Circuits Conference. San Antonio, TX, USA. 2017: 1-4.

    [12] [12] WANG D, CHEN H, LUAN W, et al. A 4-40 Gb/s PAM4 transmitter with a hybrid driver in 65 nm CMOS technology [C] // IEEE International Midwest Symposium on Circuits and Systems. Dallas, TX,USA. 2019: 251-254.

    [13] [13] CHOUDHARY M S, PUDI N S A K, REDOUTE J M, et al. An EMI immune PAM4 transmitter in 130nm BiCMOS technology [C] // IEEE MTT-S International Microwave and RF Conference. Mumbai,India. 2019: 1-4.

    [14] [14] LIM B, KIM D, YOO C. Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture [J].Electronics Letters, 2020, 56(9): 431-432.

    [15] [15] KIM J, KUNDU S, BALANKUTTY A, et al. A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET [J]. IEEE J Sol Sta Circ, 2021, 57(1): 6-20.

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    WANG Xinwu, ZHANG Changchun, ZHANG Yi, WANG Jing. Design of 56 Gbit/s Low-Power PAM4 SerDes Transmitter with Fractionally-Spaced FFE[J]. Microelectronics, 2024, 54(2): 235

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    Paper Information

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    Received: Aug. 2, 2023

    Accepted: --

    Published Online: Aug. 21, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230299

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