Microelectronics, Volume. 52, Issue 4, 675(2022)

Design and Implementation of a High Security and High Performance RSA Coprocessor

ZANG Shiping, XU Kejing, HU Yi, DU Pengcheng, and GAO Ying
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    References(5)

    [1] [1] WANG D M, DING Y Y, ZHANG J, et al. Area-efficient and ultra-low power architecture of RSA processor for RFID [J]. Elec Lett, 2012, 48(19): 1185-1187.

    [2] [2] HUANG Z, LI S G. Design and implementation of a low power RSA process for smartcard [J]. Int J Modern Edu Comput Sci, 2011, 3(3): 8-14.

    [8] [8] ZHENG X J, LIU Z X, PENG B. Design and implementation of an ultra low power RSA coprocessor [C]// WiCom. Dalian, China. 2008: 1-5.

    [9] [9] WERNER F T, DJORDJEVIC A R, ZAJIC A G. A compact probe for EM side-channel attacks on cryptographic systems [C]// IEEE Int Symp Antennas Propag USNC-URSI Radio Sci Meet. Atlanta, GA, USA. 2019: 613-614.

    [12] [12] MATTHEWS A. Low cost attacks on smart cards: the electromagnetic sidechannel [J]. Next Generation Security Software, 2006: 1-14.

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    ZANG Shiping, XU Kejing, HU Yi, DU Pengcheng, GAO Ying. Design and Implementation of a High Security and High Performance RSA Coprocessor[J]. Microelectronics, 2022, 52(4): 675

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    Paper Information

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    Received: Oct. 15, 2021

    Accepted: --

    Published Online: Jan. 18, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210393

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