Fig. 1. The strategy of etching oxide mask in the DRAM capacitor.

Fig. 2. The XSEM of (a) 30 s partial etch in EB step, (b) 30 s partial etch in ME step.

Fig. 3. The XSEM of various profiles with the condition of (a) 30 s EB + 51 s ME, 77% B/T ratio, (b) 60 s EB + 36 s ME, 70% B/T ratio, (c) 90 s EB + 21 s ME, 52% B/T ratio.

Fig. 4. (a) The DARC remaining issue. (b) The SEM cross section with the conditio of “40 s EB + 0 s ME + 100 s Strip”.

Fig. 5. The SEM top view of the SiO_x mask with the condition of (a) 0 s EB + 30 s ME, (b) 30 s EB + 0 s ME, (c, d) 40 s EB + 0 s ME, (e) 50 s EB + 0 s ME, (f) 60 s EB + 0 s ME.

Fig. 6. The trend of SiO_x mask CD (current CD, blue one, left axis) and capacitor CD (final CD, red one, right axis) with CH₂F₂ flow.

Fig. 7. The blanket Si₃N₄ ER of EB step.

Fig. 8. (Color online) The mechanism of reversed CD trend.