Fig. 1. APD test chart in linear mode

Fig. 2. （a）Physical image of the detector，（b）Schematic setup of the detector Note：FPGA：Field programmable gate array，PGC：Pulse generating circuit，DCC：Delay chip circuit，HVC：High voltage circuit，PID：Temperature control circuit，VA：Voltage controlled attenuator，AMP：RF amplifier，HPF：High pass filter，LD：Laser，Atten：Optical attenuator，LPF：Low pass filter，PSC：Pulse shaping circuit

Fig. 3. ADF4351 output matching circuit scheme

Fig. 4. Phase noise test chart at each repetition frequency

Fig. 5. Schematic diagram of the waveform of the combined action of the bias voltage and the gate signal

Fig. 6. Output counts of the detector at different detection efficiencies Note：Sinusoidal gated signal with a repetition frequency of 1 GHz （a）5% detection efficiency total counts，（b）5% detection efficiency dark counts，（c）10% detection efficiency total counts，（d）10% detection efficiency dark counts，（e）15% detection efficiency total counts，（f）15% detection efficiency dark counts，（g）20% detection efficiency total counts，（h）20% detection efficiency dark counts

Fig. 7. （a）APD output signal waveform at 1500 MHz gate frequency，（b）avalanche signal after low-pass filter and amplification，（c）avalanche signal count rate under different repetition frequency without light，（d）detector working at each frequency with 10% detection efficiency for 2 hours